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公开(公告)号：US20200341191A1
公开(公告)日：2020-10-29
申请号：US16856387
申请日：2020-04-23
Applicant: Ayar Labs, Inc.
Inventor： Roy Edward Meade , Chen Sun , Shahab Ardalan , John Fini , Forrest Sedgwick
Abstract: An intact semiconductor wafer (wafer) includes a plurality of die. Each die has a top layer including routings of conductive interconnect structures electrically isolated from each other by intervening dielectric material. A top surface of the top layer corresponds to a top surface of the wafer. Below the top layer, each die has a device layer including optical devices and electronic devices. Each die has a cladding layer below the device layer and on a substrate of the wafer. Each die includes a photonic test port within the device layer. For each die, a light transfer region is formed within the intact wafer to extend through the top layer to the photonic test port within the device layer. The light transfer region provides a window for transmission of light into and out of the photonic test port from and to a location on the top surface of the wafer.
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公开(公告)号：US12014962B2
公开(公告)日：2024-06-18
申请号：US18346555
申请日：2023-07-03
Applicant: Ayar Labs, Inc.
Inventor： Roy Edward Meade , Anatol Khilo , Forrest Sedgwick , Alexandra Wright
IPC: H01L21/66 , G01R31/3185 , G02B6/12 , G02B6/13 , H04B10/073 , F21V8/00 , H04B10/50
CPC classification number: H01L22/30 , G01R31/318511 , G02B6/12 , G02B6/13 , H04B10/0731 , G02B6/0028 , H04B10/503
Abstract: A semiconductor wafer includes a semiconductor chip that includes a photonic device. The semiconductor chip includes an optical fiber attachment region in which an optical fiber alignment structure is to be fabricated. The optical fiber alignment structure is not yet fabricated in the optical fiber attachment region. The semiconductor chip includes an in-plane fiber-to-chip optical coupler positioned at an edge of the optical fiber attachment region. The in-plane fiber-to-chip optical coupler is optically connected to the photonic device. A sacrificial optical structure is optically coupled to the in-plane fiber-to-chip optical coupler. The sacrificial optical structure includes an out-of-plane optical coupler configured to receive input light from a light source external to the semiconductor chip. At least a portion of the sacrificial optical structure extends through the optical fiber attachment region.
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公开(公告)号：US20210124107A1
公开(公告)日：2021-04-29
申请号：US17079357
申请日：2020-10-23
Applicant: Ayar Labs, Inc.
Inventor： Roy Edward Meade , Anatol Khilo , Forrest Sedgwick , Alexandra Wright
IPC: F21V8/00 , G02B6/12 , H04B10/073 , H04B10/50
Abstract: A semiconductor wafer includes a semiconductor chip that includes a photonic device. The semiconductor chip includes an optical fiber attachment region in which an optical fiber alignment structure is to be fabricated. The optical fiber alignment structure is not yet fabricated in the optical fiber attachment region. The semiconductor chip includes an in-plane fiber-to-chip optical coupler positioned at an edge of the optical fiber attachment region. The in-plane fiber-to-chip optical coupler is optically connected to the photonic device. A sacrificial optical structure is optically coupled to the in-plane fiber-to-chip optical coupler. The sacrificial optical structure includes an out-of-plane optical coupler configured to receive input light from a light source external to the semiconductor chip. At least a portion of the sacrificial optical structure extends through the optical fiber attachment region.
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公开(公告)号：US11694935B2
公开(公告)日：2023-07-04
申请号：US17079357
申请日：2020-10-23
Applicant: Ayar Labs, Inc.
Inventor： Roy Edward Meade , Anatol Khilo , Forrest Sedgwick , Alexandra Wright
IPC: H01L21/66 , H04B10/073 , G02B6/12 , G02B6/13 , G01R31/3185 , F21V8/00 , H04B10/50
CPC classification number: H01L22/30 , G01R31/318511 , G02B6/12 , G02B6/13 , H04B10/0731 , G02B6/0028 , H04B10/503
Abstract: A semiconductor wafer includes a semiconductor chip that includes a photonic device. The semiconductor chip includes an optical fiber attachment region in which an optical fiber alignment structure is to be fabricated. The optical fiber alignment structure is not yet fabricated in the optical fiber attachment region. The semiconductor chip includes an in-plane fiber-to-chip optical coupler positioned at an edge of the optical fiber attachment region. The in-plane fiber-to-chip optical coupler is optically connected to the photonic device. A sacrificial optical structure is optically coupled to the in-plane fiber-to-chip optical coupler. The sacrificial optical structure includes an out-of-plane optical coupler configured to receive input light from a light source external to the semiconductor chip. At least a portion of the sacrificial optical structure extends through the optical fiber attachment region.
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公开(公告)号：US11280959B2
公开(公告)日：2022-03-22
申请号：US16856387
申请日：2020-04-23
Applicant: Ayar Labs, Inc.
Inventor： Roy Edward Meade , Chen Sun , Shahab Ardalan , John Fini , Forrest Sedgwick
Abstract: An intact semiconductor wafer (wafer) includes a plurality of die. Each die has a top layer including routings of conductive interconnect structures electrically isolated from each other by intervening dielectric material. A top surface of the top layer corresponds to a top surface of the wafer. Below the top layer, each die has a device layer including optical devices and electronic devices. Each die has a cladding layer below the device layer and on a substrate of the wafer. Each die includes a photonic test port within the device layer. For each die, a light transfer region is formed within the intact wafer to extend through the top layer to the photonic test port within the device layer. The light transfer region provides a window for transmission of light into and out of the photonic test port from and to a location on the top surface of the wafer.
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Patent Agency Ranking
公开(公告)号：US20200158961A1
公开(公告)日：2020-05-21
申请号：US16683123
申请日：2019-11-13
Applicant: Ayar Labs, Inc.
Inventor： John Fini , Roy Edward Meade , Derek Van Orden , Forrest Sedgwick
Abstract: A grating coupler reflector (retro reflector) is formed within a photonics chip and includes a vertical scattering region, an optical waveguide, and a reflector. The optical waveguide is optically coupled to the vertical scattering region. The reflector is positioned at an end of the optical waveguide. The reflector is configured to reflect light that propagates through the optical waveguide from the vertical scattering region back toward the vertical scattering region. The location of the grating coupler reflector on the photonics chip is determinable by scanning a light emitting active optical fiber over the chip and detecting when light is reflected back into the active optical fiber from the grating coupler reflector. The determined location of the grating coupler reflector on the photonics chip is usable as a reference location for aligning optical fiber(s) to corresponding optical grating couplers on the photonics chip.
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公开(公告)号：US11867944B2
公开(公告)日：2024-01-09
申请号：US17701072
申请日：2022-03-22
Applicant: Ayar Labs, Inc.
Inventor： Roy Edward Meade , Chen Sun , Shahab Ardalan , John Fini , Forrest Sedgwick
CPC classification number: G02B6/12004 , G01M11/31 , G02B6/13 , H01L22/20 , H01L22/30 , G02B2006/12107 , G02B2006/12121 , G02B2006/12145 , G02B2006/12147 , G02B2006/12164
Abstract: An intact semiconductor wafer (wafer) includes a plurality of die. Each die has a top layer including routings of conductive interconnect structures electrically isolated from each other by intervening dielectric material. A top surface of the top layer corresponds to a top surface of the wafer. Below the top layer, each die has a device layer including optical devices and electronic devices. Each die has a cladding layer below the device layer and on a substrate of the wafer. Each die includes a photonic test port within the device layer. For each die, a light transfer region is formed within the intact wafer to extend through the top layer to the photonic test port within the device layer. The light transfer region provides a window for transmission of light into and out of the photonic test port from and to a location on the top surface of the wafer.
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公开(公告)号：US20230343655A1
公开(公告)日：2023-10-26
申请号：US18346555
申请日：2023-07-03
Applicant: Ayar Labs, Inc.
Inventor： Roy Edward Meade , Anatol Khilo , Forrest Sedgwick , Alexandra Wright
IPC: H01L21/66 , H04B10/073 , G02B6/12 , G02B6/13 , G01R31/3185
CPC classification number: H01L22/30 , H04B10/0731 , G02B6/12 , G02B6/13 , G01R31/318511 , G02B6/0028
Abstract: A semiconductor wafer includes a semiconductor chip that includes a photonic device. The semiconductor chip includes an optical fiber attachment region in which an optical fiber alignment structure is to be fabricated. The optical fiber alignment structure is not yet fabricated in the optical fiber attachment region. The semiconductor chip includes an in-plane fiber-to-chip optical coupler positioned at an edge of the optical fiber attachment region. The in-plane fiber-to-chip optical coupler is optically connected to the photonic device. A sacrificial optical structure is optically coupled to the in-plane fiber-to-chip optical coupler. The sacrificial optical structure includes an out-of-plane optical coupler configured to receive input light from a light source external to the semiconductor chip. At least a portion of the sacrificial optical structure extends through the optical fiber attachment region.
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公开(公告)号：US20220214497A1
公开(公告)日：2022-07-07
申请号：US17701072
申请日：2022-03-22
Applicant: Ayar Labs, Inc.
Inventor： Roy Edward Meade , Chen Sun , Shahab Ardalan , John Fini , Forrest Sedgwick
Abstract: An intact semiconductor wafer (wafer) includes a plurality of die. Each die has a top layer including routings of conductive interconnect structures electrically isolated from each other by intervening dielectric material. A top surface of the top layer corresponds to a top surface of the wafer. Below the top layer, each die has a device layer including optical devices and electronic devices. Each die has a cladding layer below the device layer and on a substrate of the wafer. Each die includes a photonic test port within the device layer. For each die, a light transfer region is formed within the intact wafer to extend through the top layer to the photonic test port within the device layer. The light transfer region provides a window for transmission of light into and out of the photonic test port from and to a location on the top surface of the wafer.
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公开(公告)号：US11137548B2
公开(公告)日：2021-10-05
申请号：US16683123
申请日：2019-11-13
Applicant: Ayar Labs, Inc.
Inventor： John Fini , Roy Edward Meade , Derek Van Orden , Forrest Sedgwick
Abstract: A grating coupler reflector (retro reflector) is formed within a photonics chip and includes a vertical scattering region, an optical waveguide, and a reflector. The optical waveguide is optically coupled to the vertical scattering region. The reflector is positioned at an end of the optical waveguide. The reflector is configured to reflect light that propagates through the optical waveguide from the vertical scattering region back toward the vertical scattering region. The location of the grating coupler reflector on the photonics chip is determinable by scanning a light emitting active optical fiber over the chip and detecting when light is reflected back into the active optical fiber from the grating coupler reflector. The determined location of the grating coupler reflector on the photonics chip is usable as a reference location for aligning optical fiber(s) to corresponding optical grating couplers on the photonics chip.
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