Invention Grant
- Patent Title: Multi-faceted integrated-circuit dice and packages
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Application No.: US16818558Application Date: 2020-03-13
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Publication No.: US11289427B2Publication Date: 2022-03-29
- Inventor: Bok Eng Cheah , Jackson Chung Peng Kong , Jenny Shio Yin Ong , Seok Ling Lim
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Priority: MYPI2019003289 20190611
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/538 ; H01L23/48

Abstract:
A faceted integrated-circuit die includes a concave facet with an increased interconnect breakout area available to an adjacent device such as a rectangular IC die that is nested within the form factor of the concave facet. The concave facet form factor includes a ledge facet and a main-die facet. Multiple nested faceted IC dice are disclosed for increasing interconnect breakout areas and package miniaturization. A faceted silicon interposer has a concave facet that also provides an increased interconnect breakout area and package miniaturization.
Information query
IPC分类: