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    Package with wall-side capacitors
    4.
    发明授权
    Package with wall-side capacitors 有权

    公开(公告)号：US11158568B2

    公开(公告)日：2021-10-26

    申请号：US16341963

    申请日：2016-11-18

    Applicant: Intel Corporation

    Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim

    IPC: H01L23/498 ,  H05K1/11 ,  H05K3/34 ,  H01L23/00 ,  H05K3/42 ,  H05K3/46

    Abstract: An apparatus is provided which comprises: a plurality of organic dielectric layers forming a substrate, a plurality of first conductive contacts on a top surface of the substrate, a plurality of second conductive contacts on a bottom surface of the substrate, a plurality of third conductive contacts on a side wall surface of the substrate, and one or more discrete capacitor(s) coupled with the third conductive contacts on the side wall surface. Other embodiments are also disclosed and claimed.

    Plane-less voltage reference interconnects
    5.
    发明授权
    Plane-less voltage reference interconnects 有权

    公开(公告)号：US11037874B2

    公开(公告)日：2021-06-15

    申请号：US16450287

    申请日：2019-06-24

    Applicant: Intel Corporation

    Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Seok Ling Lim

    IPC: H01L23/48 ,  H01L23/522 ,  H01L23/552 ,  H01L23/528 ,  H01L23/00

    Abstract: An electronic device comprises an integrated circuit (IC) die including a first plurality of contact pads; and a plurality of stacked interconnect layers. The plurality of stacked interconnect layer include a first interconnect layer including a first conductive plane, a first vertical interconnect portion, and dielectric material isolating the first vertical interconnect portion from the first conductive plane; and a second interconnect layer including a second conductive plane contacting the first conductive plane, a second vertical interconnect portion contacting the first vertical interconnect portion, and the dielectric material isolating the second vertical interconnect portion from the second conductive plane; wherein the first and second vertical interconnect portions are included in a first vertical interconnect through the first and second conductive planes that contacts a first contact pad of the first plurality of contact pads.

    Semiconductor package with package components disposed on a package substrate within a footprint of a die
    6.
    发明授权
    Semiconductor package with package components disposed on a package substrate within a footprint of a die 有权

    公开(公告)号：US10396047B2

    公开(公告)日：2019-08-27

    申请号：US15977617

    申请日：2018-05-11

    Applicant: Intel Corporation

    Inventor： Jenny Shio Yin Ong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Seok Ling Lim

    IPC: H01L29/00 ,  H01L23/64 ,  H01L23/538 ,  H01L23/552 ,  H01L23/498

    Abstract: Embodiments of the present disclosure provide a semiconductor package configured to provide for a disposition of one or more package components on a substrate within a footprint of a package die. In embodiments, the package may include a package substrate having a first side and a second side opposite the first side. An area of the first side of the package substrate within which a die is to be disposed may form a footprint of the die on the substrate. The package may further include a voltage reference plane coupled with the second side of the package substrate. At least a portion of the voltage reference plane may be disposed within the die footprint, to provide a reference voltage to components to be disposed within the footprint on the second side of the substrate, and to shield these components from electromagnetic interference. Other embodiments may be described and/or claimed.

    INTEGRATED CIRCUIT PACKAGES WITH CONDUCTIVE ELEMENT HAVING CAVITIES HOUSING ELECTRICALLY CONNECTED EMBEDDED COMPONENTS
    7.
    发明申请
    INTEGRATED CIRCUIT PACKAGES WITH CONDUCTIVE ELEMENT HAVING CAVITIES HOUSING ELECTRICALLY CONNECTED EMBEDDED COMPONENTS 审中-公开

    公开(公告)号：US20180342467A1

    公开(公告)日：2018-11-29

    申请号：US15974393

    申请日：2018-05-08

    Applicant: Intel Corporation

    Inventor： Seok Ling Lim ,  Jenny Shio Yin Ong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

    IPC: H01L23/00 ,  H01L23/528 ,  H01L49/02

    Abstract: Disclosed herein are integrated circuit (IC) structures with a conductive element coupled to a first surface of a package substrate, where the conductive element has cavities for embedding components and the embedded components are electrically connected to the conductive element, as well as related apparatuses and methods. In some embodiments, embedded components have one terminal end, which may be positioned vertically, with the terminal end facing into the cavity, and coupled to the conductive element. In some embodiments, embedded components have two terminal ends, which may be positioned vertically with one terminal end coupled to the conductive element and the other terminal end coupled to the package substrate. In some embodiments, embedded components include passive devices, such as capacitors, resistors, and inductors. In some embodiments, a conductive element is a stiffener.

    Hybrid boards with embedded planes
    8.
    发明授权
    Hybrid boards with embedded planes 有权

    公开(公告)号：US12256487B2

    公开(公告)日：2025-03-18

    申请号：US17367674

    申请日：2021-07-06

    Applicant: Intel Corporation

    Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Chin Lee Kuan ,  Tin Poay Chuah

    IPC: H05K1/02 ,  H05K3/46

    Abstract: The present disclosure is directed to a hybrid dielectric interconnect stack for a printed circuit board having a first dielectric layer with a first dielectric constant and a first dielectric loss tangent positioned over an intermediate layer, which includes a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent, an embedded conductive layer, and a second dielectric sublayer with a second sublayer dielectric constant and a second sublayer dielectric loss tangent, in which the embedded conductive layer is positioned between the first and second dielectric sublayers, and a second dielectric layer with a second dielectric constant and a second dielectric loss tangent, in which the intermediate layer is positioned between the first and second dielectric layers.

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