-
公开(公告)号:US11527485B2
公开(公告)日:2022-12-13
申请号:US17088618
申请日:2020-11-04
Applicant: Intel Corporation
Inventor: Seok Ling Lim , Bok Eng Cheah , Jenny Shio Yin Ong , Jackson Chung Peng Kong , Kooi Chi Ooi
IPC: H01L23/552 , H01L23/495 , H01L23/00
Abstract: The present disclosure relates to a semiconductor package that may include a substrate, an interposer coupled to the substrate, a shield frame including at least one frame recess and at least one opening positioned over the interposer, a conductive shield layer on the shield frame, and a plurality of components coupled to the interposer.
-
公开(公告)号:US11527463B2
公开(公告)日:2022-12-13
申请号:US16984173
申请日:2020-08-04
Applicant: Intel Corporation
Inventor: Bok Eng Cheah , Jenny Shio Yin Ong , Seok Ling Lim , Kooi Chi Ooi , Jackson Chung Peng Kong
IPC: H01L23/498 , H01L21/48 , H01L23/522
Abstract: According to various examples, a semiconductor package is described including a substrate raiser with interconnect vias that may be positioned on the bottom side of a substrate and mini solder balls positioned on the interconnect vias and a plurality of large solder balls positioned on the bottom side of the substrate adjacent to the substrate raiser, wherein the mini solder balls and the large solder balls extend approximately a same height from the substrate for mounting on a printed circuit board.
-
公开(公告)号:US20210375735A1
公开(公告)日:2021-12-02
申请号:US16984173
申请日:2020-08-04
Applicant: Intel Corporation
Inventor: Bok Eng Cheah , Jenny Shio Yin Ong , Seok Ling Lim , Kooi Chi Ooi , Jackson Chung Peng Kong
IPC: H01L23/498 , H01L23/522 , H01L21/48
Abstract: According to various examples, a semiconductor package is described including a substrate raiser with interconnect vias that may be positioned on the bottom side of a substrate and mini solder balls positioned on the interconnect vias and a plurality of large solder balls positioned on the bottom side of the substrate adjacent to the substrate raiser, wherein the mini solder balls and the large solder balls extend approximately a same height from the substrate for mounting on a printed circuit board.
-
公开(公告)号:US11158568B2
公开(公告)日:2021-10-26
申请号:US16341963
申请日:2016-11-18
Applicant: Intel Corporation
Inventor: Jenny Shio Yin Ong , Seok Ling Lim
Abstract: An apparatus is provided which comprises: a plurality of organic dielectric layers forming a substrate, a plurality of first conductive contacts on a top surface of the substrate, a plurality of second conductive contacts on a bottom surface of the substrate, a plurality of third conductive contacts on a side wall surface of the substrate, and one or more discrete capacitor(s) coupled with the third conductive contacts on the side wall surface. Other embodiments are also disclosed and claimed.
-
公开(公告)号:US11037874B2
公开(公告)日:2021-06-15
申请号:US16450287
申请日:2019-06-24
Applicant: Intel Corporation
Inventor: Bok Eng Cheah , Jackson Chung Peng Kong , Jenny Shio Yin Ong , Seok Ling Lim
IPC: H01L23/48 , H01L23/522 , H01L23/552 , H01L23/528 , H01L23/00
Abstract: An electronic device comprises an integrated circuit (IC) die including a first plurality of contact pads; and a plurality of stacked interconnect layers. The plurality of stacked interconnect layer include a first interconnect layer including a first conductive plane, a first vertical interconnect portion, and dielectric material isolating the first vertical interconnect portion from the first conductive plane; and a second interconnect layer including a second conductive plane contacting the first conductive plane, a second vertical interconnect portion contacting the first vertical interconnect portion, and the dielectric material isolating the second vertical interconnect portion from the second conductive plane; wherein the first and second vertical interconnect portions are included in a first vertical interconnect through the first and second conductive planes that contacts a first contact pad of the first plurality of contact pads.
-
公开(公告)号:US10396047B2
公开(公告)日:2019-08-27
申请号:US15977617
申请日:2018-05-11
Applicant: Intel Corporation
Inventor: Jenny Shio Yin Ong , Bok Eng Cheah , Jackson Chung Peng Kong , Seok Ling Lim
IPC: H01L29/00 , H01L23/64 , H01L23/538 , H01L23/552 , H01L23/498
Abstract: Embodiments of the present disclosure provide a semiconductor package configured to provide for a disposition of one or more package components on a substrate within a footprint of a package die. In embodiments, the package may include a package substrate having a first side and a second side opposite the first side. An area of the first side of the package substrate within which a die is to be disposed may form a footprint of the die on the substrate. The package may further include a voltage reference plane coupled with the second side of the package substrate. At least a portion of the voltage reference plane may be disposed within the die footprint, to provide a reference voltage to components to be disposed within the footprint on the second side of the substrate, and to shield these components from electromagnetic interference. Other embodiments may be described and/or claimed.
-
7.
公开(公告)号:US20180342467A1
公开(公告)日:2018-11-29
申请号:US15974393
申请日:2018-05-08
Applicant: Intel Corporation
Inventor: Seok Ling Lim , Jenny Shio Yin Ong , Bok Eng Cheah , Jackson Chung Peng Kong
IPC: H01L23/00 , H01L23/528 , H01L49/02
Abstract: Disclosed herein are integrated circuit (IC) structures with a conductive element coupled to a first surface of a package substrate, where the conductive element has cavities for embedding components and the embedded components are electrically connected to the conductive element, as well as related apparatuses and methods. In some embodiments, embedded components have one terminal end, which may be positioned vertically, with the terminal end facing into the cavity, and coupled to the conductive element. In some embodiments, embedded components have two terminal ends, which may be positioned vertically with one terminal end coupled to the conductive element and the other terminal end coupled to the package substrate. In some embodiments, embedded components include passive devices, such as capacitors, resistors, and inductors. In some embodiments, a conductive element is a stiffener.
-
公开(公告)号:US12256487B2
公开(公告)日:2025-03-18
申请号:US17367674
申请日:2021-07-06
Applicant: Intel Corporation
Inventor: Jackson Chung Peng Kong , Bok Eng Cheah , Jenny Shio Yin Ong , Seok Ling Lim , Chin Lee Kuan , Tin Poay Chuah
Abstract: The present disclosure is directed to a hybrid dielectric interconnect stack for a printed circuit board having a first dielectric layer with a first dielectric constant and a first dielectric loss tangent positioned over an intermediate layer, which includes a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent, an embedded conductive layer, and a second dielectric sublayer with a second sublayer dielectric constant and a second sublayer dielectric loss tangent, in which the embedded conductive layer is positioned between the first and second dielectric sublayers, and a second dielectric layer with a second dielectric constant and a second dielectric loss tangent, in which the intermediate layer is positioned between the first and second dielectric layers.
-
公开(公告)号:US20240222346A1
公开(公告)日:2024-07-04
申请号:US18091228
申请日:2022-12-29
Applicant: Intel Corporation
Inventor: Bok Eng Cheah , Seok Ling Lim , Jenny Shio Yin Ong , Kooi Chi Ooi , Jackson Chung Peng Kong
CPC classification number: H01L25/18 , H01L21/56 , H01L23/3107 , H01L24/14 , H01L24/16 , H01L24/20 , H01L25/50 , H01L2224/1403 , H01L2224/16227 , H01L2224/211
Abstract: An apparatus is provided which comprises: a first package, a second package coupled with the first package, the second package comprising a mold layer having a recess on a first mold surface, a first plurality of devices adjacent to the recess and a metal redistribution layer (RDL) coupled to a second mold surface opposite the first mold surface, wherein the mold layer includes a first thickness, wherein the recess includes a second thickness, and wherein the second thickness is less than the first thickness, and an integrated circuit device coupled with both the second package at the recess and with the first package through a plurality of solder bumps. Other embodiments are also disclosed and claimed.
-
公开(公告)号:US20230048835A1
公开(公告)日:2023-02-16
申请号:US17975223
申请日:2022-10-27
Applicant: Intel Corporation
Inventor: Bok Eng Cheah , Jackson Chung Peng Kong , Jenny Shio Yin Ong , Ping Ping Ooi , Seok Ling Lim
IPC: H01L23/538 , H01L21/56 , H01L23/31 , H01L23/00 , H01L25/065 , H01L25/00
Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.
-
-
-
-
-
-
-
-
-