Invention Grant
- Patent Title: Integration of graphene and boron nitride hetero-structure device over semiconductor layer
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Application No.: US16501731Application Date: 2019-05-28
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Publication No.: US11296237B2Publication Date: 2022-04-05
- Inventor: Archana Venugopal , Luigi Colombo , Arup Polley
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Andrew R. Ralston; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/20 ; H01L29/267 ; H01L29/49 ; H01L29/45 ; H01L29/66 ; H01L21/02 ; H01L21/8258 ; H01L27/092 ; H01L29/16
Abstract:
A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.
Public/Granted literature
- US20190288122A1 Integration of graphene and boron nitrite hetero-structure device over semiconductor layer Public/Granted day:2019-09-19
Information query
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