公开(公告)号：US12139569B2

公开(公告)日：2024-11-12

申请号：US17675055

申请日：2022-02-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo

IPC: C08F292/00 ,  C08F8/42 ,  C08J5/00 ,  C08K3/04 ,  C08K3/08 ,  C08K7/00 ,  C08L25/06 ,  C08L33/12 ,  G03F1/78

Abstract: A method of forming a composite material includes photo-initiating a polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice. Unpolymerized monomer is removed from the polymer microlattice. The polymer microlattice is coated with a metal. The metal-coated polymer microlattice is dispersed in a polymer matrix.

公开(公告)号：US11710764B2

公开(公告)日：2023-07-25

申请号：US16020131

申请日：2018-06-27

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Sagnik Dey ,  Luigi Colombo ,  Haowen Bu ,  Scott Robert Summerfelt ,  Mark Robert Visokay ,  John Paul Campbell

IPC: H01L21/285 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/306

CPC classification number: H01L28/91 ,  H01L21/28518 ,  H01L21/306 ,  H01L21/32133

Abstract: An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.

公开(公告)号：US11296237B2

公开(公告)日：2022-04-05

申请号：US16501731

申请日：2019-05-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Archana Venugopal ,  Luigi Colombo ,  Arup Polley

IPC: H01L29/786 ,  H01L29/20 ,  H01L29/267 ,  H01L29/49 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/16

Abstract: A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.

公开(公告)号：US20210272804A1

公开(公告)日：2021-09-02

申请号：US17315524

申请日：2021-05-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L23/373 ,  H01L21/56 ,  H01L23/433 ,  H01L23/367

Abstract: A packaged electronic device includes an integrated circuit and an electrically non-conductive encapsulation material in contact with the integrated circuit. A thermal conduit extends from an exterior of the package, through the encapsulation material, to the integrated circuit. The thermal conduit has a thermal conductivity higher than the encapsulation material contacting the thermal conduit. The thermal conduit includes a cohered nanoparticle film. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US11063120B2

公开(公告)日：2021-07-13

申请号：US16232123

申请日：2018-12-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Luigi Colombo ,  Archana Venugopal ,  Benjamin Stassen Cook ,  Nazila Dadvand

IPC: H01L29/16 ,  H01L21/768 ,  C01B32/194 ,  H01L23/532 ,  H01L27/06 ,  H01L29/06 ,  C23C16/26 ,  H01L21/02 ,  C01B32/184 ,  C25D11/00 ,  C23C16/02 ,  B05D1/00 ,  H01L23/00

Abstract: A structure includes a metal layer and a plurality of interconnected unit cells forming a lattice contained at least partly within the metal layer, including at least a first unit cell formed of first interconnected graphene tubes, and a second unit cell formed of second interconnected graphene tubes, wherein the metal layer protrudes through holes within the lattice.

公开(公告)号：US20210202688A1

公开(公告)日：2021-07-01

申请号：US17181485

申请日：2021-02-22

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L49/02 ,  H01L21/02 ,  H01L27/06 ,  H01G4/08 ,  H01L29/06

Abstract: In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V2; and a capacitor second plate over the dielectric stack.

公开(公告)号：US20200381517A1

公开(公告)日：2020-12-03

申请号：US16995563

申请日：2020-08-17

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Luigi Colombo ,  Nazila Dadvand ,  Archana Venugopal

IPC: H01L29/15 ,  H01L29/16 ,  H01L29/808 ,  H01L29/423

Abstract: A switchable array includes: a microstructure of interconnected units formed of graphene tubes with open spaces in the microstructure bounded by the graphene tubes; at least one JFET gate in at least one of the graphene tubes; and a control line having an end connected to the at least one JFET gate. The control line extends to a periphery of the microstructure.

公开(公告)号：US10790228B2

公开(公告)日：2020-09-29

申请号：US16372455

申请日：2019-04-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L21/288 ,  H01L23/367 ,  H01L23/373 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/324 ,  H01L21/285 ,  H01L21/3205 ,  H01L23/48

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

公开(公告)号：US10748999B2

公开(公告)日：2020-08-18

申请号：US16229827

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Luigi Colombo ,  Nazila Dadvand ,  Archana Venugopal

IPC: H01L29/15 ,  H01L29/16 ,  H01L29/423 ,  H01L29/808 ,  H01L29/66

Abstract: A switchable array micro-lattice comprises a plurality of interconnected units wherein the units are formed of graphene tubes. JFET gates are provided in selected members of the micro-lattice. Gate connectors are routed from an external surface of an integrated circuit (IC) through openings in the micro-lattice to permit control of the JFET gates.

公开(公告)号：US10181516B2

公开(公告)日：2019-01-15

申请号：US15865795

申请日：2018-01-09

Applicant: Texas Instruments Incorporated

Inventor： Luigi Colombo ,  Archana Venugopal

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/786 ,  H01L51/00 ,  H01L51/05 ,  H01L29/66 ,  H01L29/45 ,  H01L21/02 ,  H01L29/778 ,  H01L29/51

Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function