公开(公告)号：US11984475B2

公开(公告)日：2024-05-14

申请号：US17536391

申请日：2021-11-29

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Joseph Maurice Khayat ,  Archana Venugopal

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/861

CPC classification number: H01L29/0626 ,  H01L29/66113 ,  H01L29/861

Abstract: An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.

公开(公告)号：US20240153841A1

公开(公告)日：2024-05-09

申请号：US18544590

申请日：2023-12-19

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Archana Venugopal ,  Daniel Lee Revier

IPC: H01L23/373 ,  H01L21/3205 ,  H01L21/683 ,  H01L21/78 ,  H01L23/532

CPC classification number: H01L23/373 ,  H01L21/32051 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/53209

Abstract: In described examples, a method comprises forming a patterned region on a first surface of the semiconductor substrate. The method also comprises forming circuitry in the patterned region. The method further comprises forming a metallic layer on a second surface of the semiconductor substrate, in which the second surface opposes the first surface; and forming a carbon layer on the metallic layer.

公开(公告)号：US11938715B2

公开(公告)日：2024-03-26

申请号：US16229668

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Luigi Colombo ,  Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal

IPC: B32B9/00 ,  B32B9/04 ,  C01B32/184 ,  C01B32/19 ,  C23C18/32 ,  C23C18/38 ,  H01M50/00 ,  B82Y30/00

CPC classification number: B32B9/007 ,  B32B9/041 ,  B32B9/045 ,  C01B32/184 ,  C01B32/19 ,  C23C18/32 ,  C23C18/38 ,  H01M50/00 ,  B32B2305/38 ,  B32B2457/14 ,  B82Y30/00 ,  C01P2002/20 ,  Y10T428/30

Abstract: A microstructure comprises a plurality of interconnected units wherein the units are formed of graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice.

公开(公告)号：US20230411302A1

公开(公告)日：2023-12-21

申请号：US17806954

申请日：2022-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： James Todd ,  Archana Venugopal

IPC: H01L23/552 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L23/552 ,  H01L27/0629 ,  H01L28/91

Abstract: A semiconductor device is described here. The semiconductor device includes a buried layer of a first conductivity type disposed on a semiconductor substrate. The semiconductor device includes a deep trench bypass capacitor extending into the buried layer and terminating in the buried layer. The deep trench bypass capacitor of the semiconductor device includes a first doped region, a dielectric disposed around the first doped region, and a second doped region disposed around the dielectric.

公开(公告)号：US20230170384A1

公开(公告)日：2023-06-01

申请号：US17536391

申请日：2021-11-29

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Joseph Maurice Khayat ,  Archana Venugopal

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/66

CPC classification number: H01L29/0626 ,  H01L29/861 ,  H01L29/66113

Abstract: An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.

公开(公告)号：US11004680B2

公开(公告)日：2021-05-11

申请号：US15361403

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L23/373 ,  H01L21/56 ,  H01L23/433 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: A packaged electronic device includes an integrated circuit and an electrically non-conductive encapsulation material in contact with the integrated circuit. A thermal conduit extends from an exterior of the package, through the encapsulation material, to the integrated circuit. The thermal conduit has a thermal conductivity higher than the encapsulation material contacting the thermal conduit. The thermal conduit includes a cohered nanoparticle film. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US10923567B2

公开(公告)日：2021-02-16

申请号：US16792379

申请日：2020-02-17

Applicant: Texas Instruments Incorporated

Inventor： Luigi Colombo ,  Archana Venugopal

IPC: H01L29/16 ,  H01L29/786 ,  H01L51/00 ,  H01L51/05 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/417 ,  H01L21/02 ,  H01L29/51

Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function

公开(公告)号：US10804201B2

公开(公告)日：2020-10-13

申请号：US16236101

申请日：2018-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Nazila Dadvand ,  Luigi Colombo

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  C01B32/184 ,  H01L23/522

Abstract: A structure for a semiconductor device includes a dielectric layer and a metal layer. The structure also includes a plurality of unit cells. Each unit cell is formed of interconnected segments. The plurality of unit cells forms a lattice. The lattice is between the dielectric layer and the metal layer.

公开(公告)号：US20200211849A1

公开(公告)日：2020-07-02

申请号：US16810891

申请日：2020-03-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Luigi Colombo ,  Archana Venugopal

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/786 ,  H01L29/45 ,  H01L51/05 ,  H01L51/00

Abstract: A method, e.g. of forming an electronic device, includes forming a carbon-doped metal layer over a substrate. The carbon-doped metal layer is heated and cooled such that a first graphene layer is formed on a top surface of the carbon-doped metal layer, and a second graphene layer is formed between the carbon-doped metal layer and the substrate. A portion of the first graphene layer is removed and a portion of the carbon-doped metal layer is removed, thereby forming first and second spaced-apart contact layers on the second graphene layer.

公开(公告)号：US10593763B2

公开(公告)日：2020-03-17

申请号：US16211800

申请日：2018-12-06

Applicant: Texas Instruments Incorporated

Inventor： Luigi Colombo ,  Archana Venugopal

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/786 ,  H01L51/00 ,  H01L51/05 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/417 ,  H01L21/02 ,  H01L29/51

Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function