Invention Grant
- Patent Title: Embedded network on chip accessible to programmable logic fabric of programmable logic device in multi-dimensional die systems
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Application No.: US16020748Application Date: 2018-06-27
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Publication No.: US11296706B2Publication Date: 2022-04-05
- Inventor: Sean R. Atsatt , Scott J. Weber , Ravi Prakash Gutala , Aravind Raghavendra Dasu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Fletcher Yoder, P.C.
- Main IPC: H03K19/17772
- IPC: H03K19/17772 ; H03K19/1776 ; H03K19/17768 ; H03K19/17796 ; H03K19/17758

Abstract:
An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.
Public/Granted literature
Information query
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