利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

29 条记录 (耗时 0.014 秒)

    MULTI-PURPOSE INTERFACE FOR CONFIGURATION DATA AND USER FABRIC DATA
    2.
    发明申请
    MULTI-PURPOSE INTERFACE FOR CONFIGURATION DATA AND USER FABRIC DATA 审中-公开

    公开(公告)号：US20190140648A1

    公开(公告)日：2019-05-09

    申请号：US16235984

    申请日：2018-12-28

    申请人： Intel Corporation

    发明人： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

    IPC分类号： H03K19/177 ,  H01L25/065 ,  G11C7/10

    摘要： An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.

    Sector-Aligned Memory Accessible to Programmable Logic Fabric of Programmable Logic Device
    3.
    发明申请
    Sector-Aligned Memory Accessible to Programmable Logic Fabric of Programmable Logic Device 审中-公开

    公开(公告)号：US20190043536A1

    公开(公告)日：2019-02-07

    申请号：US15868304

    申请日：2018-01-11

    申请人： Intel Corporation

    发明人： Scott J. Weber ,  Sean R. Atsatt ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Jun Pin Tan

    IPC分类号： G11C5/02 ,  G11C5/06 ,  H03K19/177

    摘要： An integrated circuit device may include programmable logic fabric on a first integrated circuit die and sector-aligned memory on a second integrated circuit die to enable large amounts of data to be rapidly processed by a sector of programmable logic of the programmable logic device. The programmable logic fabric may include a first and second sectors. The first sector may be programmed with a circuit design that operates on a first set of data. The sector-aligned memory may include a first sector of sector-aligned memory directly accessible by the first sector of programmable logic fabric and a second sector of sector-aligned memory directly accessible by the second sector of programmable logic fabric. The first sector of sector-aligned memory may store the first set of data.

    FAST MEMORY FOR PROGRAMMABLE DEVICES
    5.
    发明申请
    FAST MEMORY FOR PROGRAMMABLE DEVICES 有权

    公开(公告)号：US20210384912A1

    公开(公告)日：2021-12-09

    申请号：US17407700

    申请日：2021-08-20

    申请人： Intel Corporation

    发明人： Scott Jeremy Weber ,  Aravind Raghavendra Dasu ,  Mahesh A. Iyer ,  Patrick Koeberl

    IPC分类号： H03K19/17756 ,  H01L25/065 ,  H01L25/00

    摘要： An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface.

    Dynamic deep learning processor architecture
    8.
    发明授权
    Dynamic deep learning processor architecture 有权

    公开(公告)号：US11442889B2

    公开(公告)日：2022-09-13

    申请号：US16146886

    申请日：2018-09-28

    申请人： Intel Corporation

    发明人： Eriko Nurvitadhi ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

    IPC分类号： G06F15/76 ,  G06N3/08 ,  G06N3/063 ,  G06N3/04

    摘要： Methods and systems for dynamically reconfiguring a deep learning processor by operating the deep learning processor using a first configuration. The deep learning processor then tracking one or more parameters of a deep learning program executed using the deep learning processor in the first configuration. The deep learning processor then reconfigures the deep learning processor to a second configuration to enhance efficiency of the deep learning processor executing the deep learning program based at least in part on the one or more parameters.