公开(公告)号：US11916811B2

公开(公告)日：2024-02-27

申请号：US18177417

申请日：2023-03-02

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H04L49/109 ,  H04L49/15 ,  H01L25/065 ,  H01L23/538

CPC classification number: H04L49/109 ,  H01L25/0652 ,  H04L49/15 ,  H01L23/5386 ,  H01L2225/06513 ,  H01L2225/06517

Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

公开(公告)号：US20230253965A1

公开(公告)日：2023-08-10

申请号：US18300330

申请日：2023-04-13

Applicant: Intel Corporation

Inventor： Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Sean R. Atsatt ,  Scott J. Weber

IPC: H03K19/0175 ,  G06F3/06 ,  G11C11/417 ,  H01L25/18 ,  H01L27/02 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367 ,  G11C7/10 ,  H03K19/17796

CPC classification number: H03K19/017581 ,  G06F3/0632 ,  G06F3/0679 ,  G11C11/417 ,  H01L25/18 ,  H01L27/0207 ,  H01L23/481 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/17 ,  H01L25/50 ,  H01L24/81 ,  H01L23/3675 ,  H01L23/5385 ,  G06F3/0604 ,  G11C7/10 ,  H03K19/17796 ,  H01L2924/14335 ,  H01L2224/1703 ,  H01L2224/8112 ,  H01L2224/16225 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2924/1431 ,  H01L2924/1435 ,  H01L2924/1433 ,  H01L2924/1432 ,  G11C5/04

Abstract: An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.

公开(公告)号：US10666265B2

公开(公告)日：2020-05-26

申请号：US16146849

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Simon Chong ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Jun Pin Tan

IPC: H03K19/173 ,  G06F7/38 ,  H03K19/1776 ,  H03K19/17768 ,  H03K19/17704 ,  H03K19/17758

Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.

公开(公告)号：US20190140648A1

公开(公告)日：2019-05-09

申请号：US16235984

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H03K19/177 ,  H01L25/065 ,  G11C7/10

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.

公开(公告)号：US20190043536A1

公开(公告)日：2019-02-07

申请号：US15868304

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Scott J. Weber ,  Sean R. Atsatt ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Jun Pin Tan

IPC: G11C5/02 ,  G11C5/06 ,  H03K19/177

Abstract: An integrated circuit device may include programmable logic fabric on a first integrated circuit die and sector-aligned memory on a second integrated circuit die to enable large amounts of data to be rapidly processed by a sector of programmable logic of the programmable logic device. The programmable logic fabric may include a first and second sectors. The first sector may be programmed with a circuit design that operates on a first set of data. The sector-aligned memory may include a first sector of sector-aligned memory directly accessible by the first sector of programmable logic fabric and a second sector of sector-aligned memory directly accessible by the second sector of programmable logic fabric. The first sector of sector-aligned memory may store the first set of data.

公开(公告)号：US12063037B2

公开(公告)日：2024-08-13

申请号：US17710628

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H03K19/17772 ,  H03K19/17758 ,  H03K19/1776 ,  H03K19/17768 ,  H03K19/17796

CPC classification number: H03K19/17758 ,  H03K19/1776 ,  H03K19/17768 ,  H03K19/17772 ,  H03K19/17796

Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.

公开(公告)号：US20230244485A1

公开(公告)日：2023-08-03

申请号：US18298278

申请日：2023-04-10

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: G06F9/30 ,  G05B19/05 ,  G06N3/02 ,  G06F15/78 ,  G06F30/34 ,  G06F30/39

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G05B19/056 ,  G06N3/02 ,  G06F9/3004 ,  G06F15/7821 ,  G06F30/34 ,  G06F30/39 ,  G05B2219/21109

Abstract: An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.

公开(公告)号：US11334263B2

公开(公告)日：2022-05-17

申请号：US15868627

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Scott J. Weber ,  David Greenhill ,  Sean R. Atsatt ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Jun Pin Tan

IPC: G06F3/06 ,  G06F12/0802 ,  G06F12/0873 ,  H03K19/17736 ,  G11C7/22 ,  G11C5/02 ,  G06F12/0875 ,  G06F30/34 ,  G11C5/04 ,  G11C7/10

Abstract: An integrated circuit device may cache configuration data to enable rapid configuration from fabric cache memory. The integrated circuit device may include programmable logic fabric having configuration memory and programmable logic elements controlled by the configuration memory, and sector-aligned memory apart from the programmable logic fabric. A first sector of the configuration memory may be programmed with first configuration data. The sector-aligned memory may include a first sector of sector-aligned memory that may cache the first configuration data while the configuration memory is programmed with the first configuration data a first time. A second sector of sector-aligned memory may cache second configuration data for a second sector of the configuration memory in parallel while the first sector of sector-aligned memory caches the first configuration data for the first sector of the configuration memory.

公开(公告)号：US10423747B2

公开(公告)日：2019-09-24

申请号：US15422834

申请日：2017-02-02

Applicant: Intel Corporation

Inventor： Scott J. Weber ,  Carl Ebeling

IPC: G06F17/50

Abstract: A method for designing a system on a target device includes modifying a circuit to enable the circuit to support a plurality of threads at an instant of time. An interface is generated that enables one or more of the plurality of threads to be swapped out of an execution queue for accessing the circuit and that enables one or more other threads to be swapped into the execution queue for accessing the circuit, wherein at least one of the modifying and the generating is performed by a processor.

公开(公告)号：US20190230049A1

公开(公告)日：2019-07-25

申请号：US16369889

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H04L12/933 ,  H01L25/065

Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.