Systems and methods for an interface with a widened interface-to-fabric shoreline between semiconductor circuits and a narrower interface-to-memory controller shoreline. The interface providing transitions from a first clock of a first circuit (e.g., field-programmable gate array (FPGA)), a second clock of a second circuit (e.g., high-bandwidth memory generation 2 (HBM2) stack, and a third clock of a physical layer of the second circuit. A first transfer between the first clock and the second clock may use a first set of first-in first-outs (FIFO) buffers, such as rate-matching FIFO buffers. A second transfer between the second clock and the third clock may use a second set of FIFO buffers, such as phase compensation FIFOs.