- Patent Title: Integrated assemblies comprising conductive levels having two different metal-containing structures laterally adjacent one another, and methods of forming integrated assemblies
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Application No.: US16585418Application Date: 2019-09-27
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Publication No.: US11302707B2Publication Date: 2022-04-12
- Inventor: John D. Hopkins , Jordan D. Greenlee
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L27/1157
- IPC: H01L27/1157 ; H01L23/528 ; H01L27/11582 ; H01L27/11556 ; H01L23/532 ; H01L21/02 ; H01L21/311 ; H01L21/28 ; H01L27/11565 ; H01L27/11519
Abstract:
Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include first regions, and include second regions laterally adjacent to the first regions. The first regions have a first vertical thickness and at least two different metal-containing materials along the first vertical thickness. The second regions have a second vertical thickness at least as large as the first vertical thickness, and have only a single metal-containing material along the second vertical thickness. Dielectric-barrier material is laterally adjacent to the first regions. Charge-blocking material is laterally adjacent to the dielectric-barrier material. Charge-storage material is laterally adjacent to the charge-blocking material. Dielectric material is laterally adjacent to the charge storage material. Channel material is laterally adjacent to the dielectric material.
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