- Patent Title: Method and structure for forming a vertical field-effect transistor
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Application No.: US16664060Application Date: 2019-10-25
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Publication No.: US11302799B2Publication Date: 2022-04-12
- Inventor: Peng Xu , Choonghyun Lee , Kangguo Cheng , Juntao Li
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis, LLP
- Agent Randall Bluestone
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/423 ; H01L29/08 ; H01L21/8238 ; H01L29/78 ; H01L21/8234

Abstract:
A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer including a first concentration of germanium on the first semiconductor layer, and forming a third semiconductor layer on the second semiconductor layer. The first and third semiconductor layers each have a concentration of germanium, which is greater than the first concentration of germanium. The first, second and third semiconductor layers are patterned into at least one fin. The method further includes covering the second semiconductor layer with a mask layer. In the method, a bottom source/drain region and a top source/drain region are simultaneously grown from the first semiconductor layer and the third semiconductor layer, respectively. The mask layer is removed from the second semiconductor layer, and a gate structure is formed on and around the second semiconductor layer.
Public/Granted literature
- US20200066881A1 METHOD AND STRUCTURE FOR FORMING A VERTICAL FIELD-EFFECT TRANSISTOR Public/Granted day:2020-02-27
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