Invention Grant
- Patent Title: Network-on-chip topology generation
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Application No.: US17152034Application Date: 2021-01-19
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Publication No.: US11310169B2Publication Date: 2022-04-19
- Inventor: Honnahuggi Harinath Venkata Naga Ambica Prasad , Nitin Kumar Agarwal , Anup Gangwar , Narayana Sri Harsha Gade , Ravishankar Sreedharan
- Applicant: Arm Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Agency: Leveque Intellectual Property Law, PC
- Main IPC: H04L49/00
- IPC: H04L49/00 ; H04L49/109 ; H04L47/2441 ; H04L43/0852 ; H04L45/12 ; H04L45/02 ; H04L45/586 ; H04L43/0894

Abstract:
The present disclosure provides a computer-based method and system for synthesizing a NoC. Traffic data is determined or received, and a baseline topology is generated or received. For each router in the baseline topology, a number of edge virtual channel (EVC) combinations is determined, the transmittablility of the traffic classes are determined, and, when the traffic classes are not transmittable, the router is identified. A traffic class affinity graph (TCAG) is generated for each identified router. Traffic class combinations are generated for the identified routers based on the TCAGs and EVC combinations. The traffic classes of the identified routers are merged based on the traffic class combinations. A final EVC combination for each identified router is determined based on the merged traffic classes. A final topology is generated based, at least in part, on the merged traffic classes and the final EVC combinations for the identified routers.
Public/Granted literature
- US20210160194A1 Network-On-Chip Topology Generation Public/Granted day:2021-05-27
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