Invention Grant
- Patent Title: Self-aligned contacts for 3D logic and memory
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Application No.: US16721583Application Date: 2019-12-19
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Publication No.: US11335599B2Publication Date: 2022-05-17
- Inventor: Lars Liebmann , Jeffrey Smith , Anton J. deVilliers , Kandabara Tapily
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522 ; H01L27/118 ; H01L21/8238 ; H01L21/822 ; H01L27/11

Abstract:
A semiconductor device includes dielectric layers and local interconnects that are stacked over a substrate alternatively, and extend along a top surface of the substrate laterally. Sidewalls of the dielectric layers and sidewalls of the local interconnects have a staircase configuration. The local interconnects are spaced apart from each other by dielectric layers and have uncovered portions by the dielectric layers. The semiconductor device also includes conductive layers selectively positioned over the uncovered portions of the local interconnects, where sidewalls of the conductive layers and sidewalls of the local interconnects are coplanar. The semiconductor device further includes isolation caps that extend from the dielectric layers. The isolation caps are positioned along sidewalls of the conductive layers and sidewalls of the local interconnects so as to separate the conductive layers from one another.
Public/Granted literature
- US20200373203A1 SELF-ALIGNED CONTACTS FOR 3D LOGIC AND MEMORY Public/Granted day:2020-11-26
Information query
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