公开(公告)号：US11810854B2

公开(公告)日：2023-11-07

申请号：US16535174

申请日：2019-08-08

Applicant: Tokyo Electron Limited

Inventor： Mark I. Gardner ,  H. Jim Fulford ,  Anton J. deVilliers

IPC: H01L23/525 ,  H01L23/522 ,  H01L21/768 ,  H01L21/8238 ,  H10N70/20

CPC classification number: H01L23/525 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5228 ,  H10N70/231

Abstract: A semiconductor device includes a first level having a plurality of transistor devices, and a first wiring level positioned over the first level. The first wiring level includes a plurality of conductive lines extending parallel to the first level, a plurality of conductive vertical interconnects extending perpendicular to the first level, and one or more programmable vertical interconnects that extend perpendicular to the first level and include a programmable material having a modifiable resistivity in that the one or more programmable vertical interconnects change between being conductive and being non-conductive according to a current pattern.

公开(公告)号：US11640937B2

公开(公告)日：2023-05-02

申请号：US17336420

申请日：2021-06-02

Applicant: Tokyo Electron Limited

Inventor： H. Jim Fulford ,  Mark I. Gardner ,  Anton J. deVilliers

IPC: H01L23/525 ,  H01L45/00

Abstract: In a method for forming a semiconductor device, a plurality of conductive lines is formed as a part of a first wiring level of the semiconductor device. The first wiring level is positioned over a first level having a plurality of transistor devices. The plurality of conductive lines extends parallel to the first level. In addition, a programmable horizontal bridge is formed that extends parallel to the first level, and electrically connects a first conductive line and a second conductive line of the plurality of conductive lines in the first wiring level. The programmable horizontal bridge is formed based on a programmable material that changes phase between a conductive state and a non-conductive state according to a current pattern delivered to the programmable horizontal bridge.

公开(公告)号：US11444082B2

公开(公告)日：2022-09-13

申请号：US17039307

申请日：2020-09-30

Applicant: Tokyo Electron Limited

Inventor： Jeffrey Smith ,  Anton J. deVilliers ,  Kandabara N. Tapily ,  Subhadeep Kal ,  Gerrit J. Leusink

IPC: H01L27/092 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/822 ,  H01L21/02 ,  H01L21/28 ,  H01L29/786 ,  H01L27/12

Abstract: Aspects of the disclosure provide a method for forming a semiconductor apparatus. The method includes forming a first field-effect transistor (FET) that includes a first gate on a substrate of the semiconductor apparatus. The method includes forming a second FET that is stacked on the first FET along a direction substantially perpendicular to the substrate and includes a second gate. The method includes forming a first routing track and a second routing track that is electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along the direction. A first conductive trace configured to conductively couple the first gate of the first FET to the first routing track can be formed. A second conductive trace configured to conductively couple the second gate of the second FET to the second routing track can be formed.

公开(公告)号：US11217583B2

公开(公告)日：2022-01-04

申请号：US16560490

申请日：2019-09-04

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton J. deVilliers ,  Kandabara Tapily

IPC: H01L27/092 ,  H01L29/423 ,  H01L23/535 ,  H01L29/417 ,  H01L23/528 ,  H01L29/08 ,  H01L21/3213 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/768 ,  H03K19/0948 ,  H01L27/02 ,  H01L29/10

Abstract: A semiconductor device is provided. The device includes a plurality of transistor pairs that are stacked over a substrate. Each of the plurality of transistor pairs includes a n-type transistor and a p-type transistor that are stacked over one another. The device also includes a plurality of gate electrodes that are stacked over the substrate with a staircase configuration. The plurality of gate electrodes are electrically coupled to gate structures of the plurality of transistor pairs. The device further includes a plurality of source/drain (S/D) local interconnects that are stacked over the substrate with a staircase configuration. The plurality of S/D local interconnects are electrically coupled to source regions and drain regions of the plurality of transistor pairs.

公开(公告)号：US11114381B2

公开(公告)日：2021-09-07

申请号：US16560544

申请日：2019-09-04

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton J. deVilliers ,  Kandabara Tapily

IPC: H01L23/528 ,  H01L29/08 ,  H01L25/065 ,  H01L27/11

Abstract: A semiconductor device is provided. The semiconductor device includes a transistor stack having a plurality of transistor pairs that are stacked over a substrate. Each transistor pair of the plurality of transistor pairs includes a n-type transistor and a p-type transistor that are stacked over one another. The plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs. The semiconductor device further includes one or more conductive planes formed over the substrate. The one or more conductive planes are positioned adjacent to the transistor stack, span a height of the transistor stack and are electrically coupled to the transistor stack.

公开(公告)号：US11069616B2

公开(公告)日：2021-07-20

申请号：US16535225

申请日：2019-08-08

Applicant: Tokyo Electron Limited

Inventor： H. Jim Fulford ,  Mark I. Gardner ,  Anton J. deVilliers

IPC: H01L23/525 ,  H01L45/00

Abstract: A semiconductor device includes a first level having a plurality of transistor devices, and a first wiring level positioned over the first level. The first wiring level includes a plurality of conductive lines extending parallel to the first level, and one or more programmable horizontal bridges extending parallel to the first level. Each of the one or more programmable horizontal bridges electrically connects two respective conductive lines of the plurality of conductive lines in the first wiring level. The one or more programmable horizontal bridges include a programmable material having a modifiable resistivity in that the one or more programmable horizontal bridges change between being conductive and being non-conductive.

公开(公告)号：US11049700B2

公开(公告)日：2021-06-29

申请号：US15719294

申请日：2017-09-28

Applicant: Tokyo Electron Limited

Inventor： Anton J. deVilliers ,  Mirko Vukovic ,  Brandon Byrns

IPC: H01J37/32 ,  H01L21/67 ,  H01L21/687 ,  H05H1/46 ,  H01L21/3065

Abstract: Systems and related methods are disclosed for atmospheric plasma processing of microelectronic workpieces, such as semiconductor wafers. For disclosed embodiments, a radio frequency (RF) generator generates an RF signal that is distributed to one or more plasma sources within a process chamber. The process chamber has an atmospheric pressure between 350 to 4000 Torr. The plasma sources are then scanned across a microelectronic workpiece to apply plasma gasses generated by the plasma generators to the microelectronic workpiece. The plasma sources can be individually scanned and/or combined in arrays for scanning across the microelectronic workpiece. Linear and/or angular movement can be applied to the plasma sources and/or the microelectronic workpiece to provide the scanning operation. Various implementations are disclosed.

公开(公告)号：US10946411B2

公开(公告)日：2021-03-16

申请号：US16247780

申请日：2019-01-15

Applicant: Tokyo Electron Limited

Inventor： Anton J. deVilliers

IPC: H01L21/00 ,  H01L21/66 ,  H04N5/232 ,  H04N5/225 ,  B05C11/10 ,  B05B12/08 ,  B05C13/02

Abstract: Techniques herein include systems and methods for dispensing liquids on a substrate with real-time coverage control and removal control. Techniques also encompass quality control of dispense systems. Systems and methods enable visual examination of liquids progressing on a surface of a substrate. This includes capturing and/or examining stroboscopic images of movement of a given liquid on a working surface of a substrate, and then generating feedback data for modifying a corresponding dispense. Dispenses can be modified by increasing/decreasing a dispense rate and increasing/decreasing a rotational velocity of a substrate. Feedback can be generated by automated and/or manual analysis of real time progression as well as post-process analysis of collections of images.

公开(公告)号：US10811265B2

公开(公告)日：2020-10-20

申请号：US16661655

申请日：2019-10-23

Applicant: Tokyo Electron Limited

Inventor： Anton J. deVilliers

IPC: G03F7/20 ,  H01L21/302 ,  H01L21/027 ,  H01L21/67 ,  H01L21/687 ,  G06F30/20 ,  G06F30/23 ,  H01L21/66 ,  G06T7/00

Abstract: Techniques herein include systems and methods for correcting pattern overlay errors by correcting or adjusting bowing of wafers. Location-specific tuning of stress on semiconductor substrates reduces overlay error. Location-specific tuning of stress independently modifies specific regions, areas, or point locations on a substrate to change wafer bow at those specific locations, which reduces overlay error on substrates, which in turn improves overlay of subsequent patterns created on the substrate. Techniques herein include receiving a substrate with some amount of overlay error, measuring bow of the substrate to map z-height deviations across the substrate, generating an overlay correction pattern, and then physically modifying internal stresses on the substrate at specific locations with modifications independent of other coordinate locations. Such modifications can include etching a backside surface of the substrate. One or more processing modules can be used for such processing.

公开(公告)号：US10712663B2

公开(公告)日：2020-07-14

申请号：US15675376

申请日：2017-08-11

Applicant: Tokyo Electron Limited

Inventor： Anton J. deVilliers ,  Ronald Nasman ,  David Travis ,  James Grootegoed ,  Norman A. Jacobson, Jr.

IPC: G03F7/16 ,  B05B9/04 ,  B05B9/047 ,  B05C11/10 ,  H01L21/027 ,  H01L21/66 ,  G03F7/30 ,  B05B9/08

Abstract: Techniques herein include a bladder-based dispense system using an elongate bladder configured to selectively expand and contract to assist with dispense actions. This dispense system compensates for filter-lag, which often accompanies fluid filtering for microfabrication. This dispense system also provides a high-purity and high precision dispense unit. A modular hydraulic unit houses the elongate bladder and hydraulic fluid in contact with an exterior surface of the bladder. When pressurized process fluid is in the elongate bladder, hydraulic controls can selectively reduce pressure on the bladder to cause expansion, and then selectively increase hydraulic pressure to assist with a dispense action.