Invention Grant
- Patent Title: Self-aligned scheme for semiconductor device and method of forming the same
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Application No.: US16932208Application Date: 2020-07-17
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Publication No.: US11342222B2Publication Date: 2022-05-24
- Inventor: Hsiu-Wen Hsueh , Cai-Ling Wu , Ya-Ching Tseng , Chii-Ping Chen , Neng-Jye Yang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522 ; H01L23/532

Abstract:
Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.
Public/Granted literature
- US20210098290A1 Self-Aligned Scheme for Semiconductor Device and Method of Forming the Same Public/Granted day:2021-04-01
Information query
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