公开(公告)号：US20240395559A1

公开(公告)日：2024-11-28

申请号：US18789403

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan Hsuan Hsu ,  Jao Sheng Huang ,  Yen-Chiu Kuo ,  Yu-Li Cheng ,  Ya Tzu Chen ,  Neng-Jye Yang ,  Chun-Li Chou

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/67 ,  H01L21/687

Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.

公开(公告)号：US20240021431A1

公开(公告)日：2024-01-18

申请号：US18361027

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan Hsuan Hsu ,  Jao Sheng Huang ,  Yen-Chiu Kuo ,  Yu-Li Cheng ,  Ya Tzu Chen ,  Neng-Jye Yang ,  Chun-Li Chou

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/67 ,  H01L21/687

CPC classification number: H01L21/31111 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/31144 ,  H01L21/0206 ,  H01L21/6708 ,  H01L21/68764

Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.

公开(公告)号：US11830770B2

公开(公告)日：2023-11-28

申请号：US17749303

申请日：2022-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Cai-Ling Wu ,  Ya-Ching Tseng ,  Chii-Ping Chen ,  Neng-Jye Yang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76834 ,  H01L21/7685 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.

公开(公告)号：US11735426B2

公开(公告)日：2023-08-22

申请号：US17401845

申请日：2021-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Li-Min Chen ,  Neng-Jye Yang ,  Ming-Hsi Yeh ,  Shun Wu Lin ,  Kuo-Bin Huang

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/267

CPC classification number: H01L21/28247 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/32134 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.

公开(公告)号：US20220277991A1

公开(公告)日：2022-09-01

申请号：US17749303

申请日：2022-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Cai-Ling Wu ,  Ya-Ching Tseng ,  Chii-Ping Chen ,  Neng-Jye Yang

IPC: H01L21/768 ,  H01L23/522

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.

公开(公告)号：US11362035B2

公开(公告)日：2022-06-14

申请号：US16814116

申请日：2020-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Chii-Ping Chen ,  Neng-Jye Yang ,  Ya-Lien Lee ,  An-Jiao Fu ,  Ya-Ching Tseng

IPC: H01L23/532 ,  H01L23/528

Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive structure is disposed within the first ILD layer. A capping layer continuously extends along a top surface of the lower conductive structure. An upper ILD structure overlies the lower conductive structure. A conductive body is disposed within the upper ILD structure. A bottom surface of the conductive body directly overlies the top surface of the lower conductive structure. A width of the bottom surface of the conductive body is less than a width of the top surface of the lower conductive structure. A diffusion barrier layer is disposed between the conductive body and the upper ILD structure. The diffusion barrier layer is laterally offset from a region disposed directly between the bottom surface of the conductive body and the top surface of the lower conductive structure by a non-zero distance.

公开(公告)号：US11342222B2

公开(公告)日：2022-05-24

申请号：US16932208

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Cai-Ling Wu ,  Ya-Ching Tseng ,  Chii-Ping Chen ,  Neng-Jye Yang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.

公开(公告)号：US11335589B2

公开(公告)日：2022-05-17

申请号：US16901757

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Wen Hsu ,  Ming-Che Ku ,  Neng-Jye Yang ,  Yu-Wen Wang

IPC: H01L21/768 ,  H01L21/02

Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.

公开(公告)号：US20210384034A1

公开(公告)日：2021-12-09

申请号：US17401845

申请日：2021-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Li-Min Chen ,  Neng-Jye Yang ,  Ming-Hsi Yeh ,  Shun Wu Lin ,  Kuo-Bin Huang

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/267

Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.

公开(公告)号：US20210366704A1

公开(公告)日：2021-11-25

申请号：US17391537

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Yao-Wen Hsu ,  Neng-Jye Yang ,  Li-Min Chen ,  Chia-Wei Wu ,  Kuan-Lin Chen ,  Kuo Bin Huang

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  G03F7/32 ,  G03F7/20 ,  G03F7/09 ,  H01L21/033

Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.