公开(公告)号：US20240079239A1

公开(公告)日：2024-03-07

申请号：US18152454

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bau-Ming Wang ,  Liang-Yin Chen ,  Wei Tse Hsu ,  Jung-Tsan Tsai ,  Ya-Ching Tseng ,  Chunyii Liu

IPC: H01L21/225 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L21/2253 ,  H01L21/30625 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/0673

Abstract: A method includes implanting impurities in a semiconductor substrate to form an etch stop region within the semiconductor substrate; forming a transistor structure on a front side of the semiconductor substrate; forming a front-side interconnect structure over the transistor structure; performing a thinning process on a back side of the semiconductor substrate to reduce a thickness of the semiconductor substrate, wherein the thinning process is slowed by the etch stop region; and forming a back-side interconnect structure over the back side of the semiconductor substrate.

公开(公告)号：US20210098290A1

公开(公告)日：2021-04-01

申请号：US16932208

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Cai-Ling Wu ,  Ya-Ching Tseng ,  Chii-Ping Chen ,  Neng-Jye Yang

IPC: H01L21/768 ,  H01L23/522

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.

公开(公告)号：US11694926B2

公开(公告)日：2023-07-04

申请号：US17032407

申请日：2020-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Chii-Ping Chen ,  Po-Hsiang Huang ,  Ya-Ching Tseng

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76844 ,  H01L21/7684 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76895 ,  H01L23/535

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a first interconnect disposed within an inter-level dielectric (ILD) structure over a substrate. A barrier layer is disposed along sidewalls of the ILD structure. The barrier layer has sidewalls defining an opening over the first interconnect. A second interconnect is disposed on the barrier layer. The second interconnect extends through the opening in the barrier layer and to the first interconnect.

公开(公告)号：US20210287994A1

公开(公告)日：2021-09-16

申请号：US16814116

申请日：2020-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Chii-Ping Chen ,  Neng-Jye Yang ,  Ya-Lien Lee ,  An-Jiao Fu ,  Ya-Ching Tseng

IPC: H01L23/532 ,  H01L23/528

Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive structure is disposed within the first ILD layer. A capping layer continuously extends along a top surface of the lower conductive structure. An upper ILD structure overlies the lower conductive structure. A conductive body is disposed within the upper ILD structure. A bottom surface of the conductive body directly overlies the top surface of the lower conductive structure. A width of the bottom surface of the conductive body is less than a width of the top surface of the lower conductive structure. A diffusion barrier layer is disposed between the conductive body and the upper ILD structure. The diffusion barrier layer is laterally offset from a region disposed directly between the bottom surface of the conductive body and the top surface of the lower conductive structure by a non-zero distance.

公开(公告)号：US20230411210A1

公开(公告)日：2023-12-21

申请号：US18447889

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Cai-Ling Wu ,  Ya-Ching Tseng ,  Chii-Ping Chen ,  Neng-Jye Yang

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76834 ,  H01L21/76897 ,  H01L21/76883 ,  H01L23/53266 ,  H01L23/5226 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/7685

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.

公开(公告)号：US20220277991A1

公开(公告)日：2022-09-01

申请号：US17749303

申请日：2022-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Cai-Ling Wu ,  Ya-Ching Tseng ,  Chii-Ping Chen ,  Neng-Jye Yang

IPC: H01L21/768 ,  H01L23/522

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.

公开(公告)号：US11362035B2

公开(公告)日：2022-06-14

申请号：US16814116

申请日：2020-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Chii-Ping Chen ,  Neng-Jye Yang ,  Ya-Lien Lee ,  An-Jiao Fu ,  Ya-Ching Tseng

IPC: H01L23/532 ,  H01L23/528

Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive structure is disposed within the first ILD layer. A capping layer continuously extends along a top surface of the lower conductive structure. An upper ILD structure overlies the lower conductive structure. A conductive body is disposed within the upper ILD structure. A bottom surface of the conductive body directly overlies the top surface of the lower conductive structure. A width of the bottom surface of the conductive body is less than a width of the top surface of the lower conductive structure. A diffusion barrier layer is disposed between the conductive body and the upper ILD structure. The diffusion barrier layer is laterally offset from a region disposed directly between the bottom surface of the conductive body and the top surface of the lower conductive structure by a non-zero distance.

公开(公告)号：US11342222B2

公开(公告)日：2022-05-24

申请号：US16932208

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Cai-Ling Wu ,  Ya-Ching Tseng ,  Chii-Ping Chen ,  Neng-Jye Yang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.

公开(公告)号：US20210335663A1

公开(公告)日：2021-10-28

申请号：US17032407

申请日：2020-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Chii-Ping Chen ,  Po-Hsiang Huang ,  Ya-Ching Tseng

IPC: H01L21/768 ,  H01L23/535

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a first interconnect disposed within an inter-level dielectric (ILD) structure over a substrate. A barrier layer is disposed along sidewalls of the ILD structure. The barrier layer has sidewalls defining an opening over the first interconnect. A second interconnect is disposed on the barrier layer. The second interconnect extends through the opening in the barrier layer and to the first interconnect.

公开(公告)号：US11830770B2

公开(公告)日：2023-11-28

申请号：US17749303

申请日：2022-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Cai-Ling Wu ,  Ya-Ching Tseng ,  Chii-Ping Chen ,  Neng-Jye Yang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76834 ,  H01L21/7685 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.