Invention Grant
- Patent Title: Memory device with improved margin and performance and methods of formation thereof
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Application No.: US17009034Application Date: 2020-09-01
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Publication No.: US11342338B2Publication Date: 2022-05-24
- Inventor: Shih-Hao Lin , Kian-Long Lim , Chih-Chuan Yang , Chia-Hao Pao , Jing-Yi Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L27/11
- IPC: H01L27/11 ; H01L29/06 ; H01L29/423 ; H01L29/786 ; H01L21/02 ; H01L21/3065 ; H01L21/308 ; H01L21/8238 ; H01L29/66

Abstract:
A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.
Public/Granted literature
- US20210098473A1 Memory Device with Improved Margin and Performance and Methods of Formation Thereof Public/Granted day:2021-04-01
Information query
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