公开(公告)号：US11942145B2

公开(公告)日：2024-03-26

申请号：US17662364

申请日：2022-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Jui-Wen Chang ,  Feng-Ming Chang ,  Kian-Long Lim ,  Kuo-Hsiu Hsu ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: G11C5/06 ,  G11C11/417 ,  H01L29/423 ,  H10B10/00

CPC classification number: G11C11/417 ,  H01L29/42392 ,  H10B10/125

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

公开(公告)号：US11682451B2

公开(公告)日：2023-06-20

申请号：US17407005

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yuan Chang ,  Kian-Long Lim ,  Jui-Lin Chen ,  Feng-Ming Chang

IPC: G11C11/419 ,  G11C11/412 ,  H10B10/00

CPC classification number: G11C11/412 ,  G11C11/419 ,  H10B10/12 ,  H10B10/18

Abstract: The current disclosure is directed to a SRAM bit cell having a reduced coupling capacitance. In a vertical direction, a wordline “WL” and a bitline “BL” of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, the WL is vertically spaced apart from the BL with one or more metallization level that none of the WL or the BL is formed from. Connection island structures or jumper structures are provided to connect the upper one of the WL or the BL to the transistors of the SRAM cell.

公开(公告)号：US20220384618A1

公开(公告)日：2022-12-01

申请号：US17877221

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Jui-Lin Chen ,  Hsin-Wen Su ,  Kian-Long Lim ,  Bwo-Ning Chen ,  Chih-Hsuan Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

公开(公告)号：US20220383943A1

公开(公告)日：2022-12-01

申请号：US17877049

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei Wang ,  Chia-Hao Pao ,  Choh Fei Yeap ,  Yu-Kuan Lin ,  Kian-Long Lim

IPC: G11C11/412 ,  H01L27/11 ,  G11C11/419

Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

公开(公告)号：US11024370B2

公开(公告)日：2021-06-01

申请号：US16587504

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kian-Long Lim ,  Chia-Hao Pao

IPC: G11C11/419 ,  G11C11/412 ,  G11C11/418

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a boost circuit configured to output a first negative voltage at a first output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit can include a transistor, and a second output terminal electrically connected to the first output terminal. The transistor can include a first source/drain terminal, a second source/drain terminal, and a gate terminal. The first source/drain terminal can be electrically coupled to the second output terminal. The second source/drain terminal can be electrically connected to a voltage source. The gate terminal can be electrically connected to a ground voltage supply.

公开(公告)号：US12160985B2

公开(公告)日：2024-12-03

申请号：US18151991

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei Wang ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Feng-Ming Chang ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Ruey-Wen Chang

IPC: G11C11/41 ,  G11C11/418 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B10/00

Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

公开(公告)号：US20240349474A1

公开(公告)日：2024-10-17

申请号：US18751938

申请日：2024-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Kian-Long Lim ,  Ping-Wei Wang ,  Lien Jung Hung ,  Ruey-Wen Chang

IPC: H10B10/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/412 ,  G11C11/417

CPC classification number: H10B10/12 ,  G11C7/12 ,  G11C8/08 ,  G11C11/412 ,  G11C11/417

Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, and first and second pass-gate (PG) transistors. A source, a drain, and a channel of the first PU transistor and a source, a drain, and a channel of the second PU transistor are collinear. A source, a drain, and a channel of the first PD transistor, a source, a drain, and a channel of the second PD transistor, a source, a drain, and a channel of the first PG transistor, and a source, a drain, and a channel of the second PG transistor are collinear.

公开(公告)号：US20240260249A1

公开(公告)日：2024-08-01

申请号：US18608199

申请日：2024-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Chuan Yang ,  Chia-Hao Pao ,  Jing-Yi Lin

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B10/125 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

公开(公告)号：US11984400B2

公开(公告)日：2024-05-14

申请号：US17303782

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yuan Chang ,  Jui-Lin Chen ,  Kian-Long Lim ,  Feng-Ming Chang

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532 ,  H01L23/535 ,  H01L27/092 ,  H10B10/00

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/53257 ,  H01L23/535 ,  H01L27/0924 ,  H10B10/12

Abstract: An SRAM device and method of forming include pass gate (PG), pull-down (PD), and pull-up (PU) transistors. A first gate line of the PG and a second gate line of the PD and the PU extend in a first direction. A common source/drain of the PG, PD, and PU transistors interposes the first and second gate lines and another source/drain of the PG transistor. A first contact extends from the common source/drain and a second contact extends from the another source/drain. A third contact is disposed above the second contact with a first width in the first direction and a first length in a second direction, first length being greater than the first width.

公开(公告)号：US11552084B2

公开(公告)日：2023-01-10

申请号：US17248112

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei Wang ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Feng-Ming Chang ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Ruey-Wen Chang

IPC: H01L27/11 ,  G11C11/41 ,  H01L23/528 ,  H01L29/06 ,  G11C11/418 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.