- 专利标题： Semiconductor device with reduced critical dimensions and method of manufacturing the same
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申请号： US16440354申请日： 2019-06-13
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公开(公告)号： US11355342B2公开(公告)日： 2022-06-07
- 发明人: Kuo-Hui Su
- 申请人： NANYA TECHNOLOGY CORPORATION
- 申请人地址： TW New Taipei
- 专利权人： NANYA TECHNOLOGY CORPORATION
- 当前专利权人： NANYA TECHNOLOGY CORPORATION
- 当前专利权人地址： TW New Taipei
- 代理机构： Muncy, Geissler, Olds & Lowe, P.C.
- 主分类号： H01L21/3115
- IPC分类号： H01L21/3115 ; H01L21/033 ; H01L21/02
摘要：
A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.
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