Invention Grant
- Patent Title: Non-vertical through-via in package
-
Application No.: US16895415Application Date: 2020-06-08
-
Publication No.: US11355406B2Publication Date: 2022-06-07
- Inventor: Cheng-Lin Huang , Jung-Hua Chang , Jy-Jie Gau , Jing-Cheng Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/498 ; H01L21/48 ; H01L23/538 ; H01L23/00 ; H01L25/10 ; H01L25/00 ; H01L21/56 ; H01L25/065

Abstract:
A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die. A plurality of redistribution lines (RDLs) extends into the dielectric layer to electrically couple to the device die and the through-via.
Public/Granted literature
- US20200303275A1 Non-Vertical Through-via in Package Public/Granted day:2020-09-24
Information query
IPC分类: