Invention Grant
- Patent Title: Package structure and manufacturing method thereof
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Application No.: US16921916Application Date: 2020-07-06
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Publication No.: US11355418B2Publication Date: 2022-06-07
- Inventor: Chen-Hua Yu , Chun-Hui Yu , Jeng-Nan Hung , Kuo-Chung Yee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L23/42
- IPC: H01L23/42 ; H01L25/065 ; H01L23/00 ; H01L23/522 ; H01L23/528 ; H01L23/31

Abstract:
A package structure includes a wafer-form semiconductor package and a thermal dissipating system. The wafer-form semiconductor package includes semiconductor dies electrically connected with each other. The thermal dissipating system is located on and thermally coupled to the wafer-form semiconductor package, where the thermal dissipating system has a hollow structure with a fluidic space, and the fluidic space includes a ceiling and a floor. The thermal dissipating system includes at least one inlet opening, at least one outlet opening and a plurality of first microstructures. The at least one inlet opening and the at least one outlet opening are spatially communicated with the fluidic space. The first microstructures are located on the floor, and at least one of the first microstructures is corresponding to the at least one outlet opening.
Public/Granted literature
- US20210098335A1 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Public/Granted day:2021-04-01
Information query
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