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    Integrated fan-out package and method for fabricating the same
    2.
    发明授权
    Integrated fan-out package and method for fabricating the same 有权

    公开(公告)号：US11211336B2

    公开(公告)日：2021-12-28

    申请号：US16671188

    申请日：2019-11-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/367 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/78

    Abstract: An integrated fan-out package includes an integrated circuit, a plurality of semiconductor devices, a first redistribution circuit structure, and an insulating encapsulation. The integrated circuit has an active surface and a rear surface opposite to the active surface. The semiconductor devices are electrically connected the integrated circuit. The first redistribution circuit structure is disposed between the integrated circuit and the semiconductor devices. The first redistribution circuit structure is electrically connected to the integrated circuit and the semiconductor devices respectively. The first redistribution circuit structure has a first surface, a second surface opposite to the first surface, and lateral sides between the first surface and the second surface. The insulating encapsulation encapsulates the integrated circuit and the semiconductor devices and covers the first surface and the second surface of the first redistribution circuit structure. Furthermore, methods for fabricating the integrated fan-out package are also provided.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210159139A1

    公开(公告)日：2021-05-27

    申请号：US16942750

    申请日：2020-07-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Jeng-Nan Hung ,  Kuo-Chung Yee ,  Po-Fan Lin

    IPC: H01L23/36 ,  H01L23/04 ,  H05K7/20

    Abstract: A semiconductor device including a substrate, a semiconductor package, a plurality of pillars and a lid is provided. The semiconductor package is disposed on the substrate and includes at least one semiconductor die. The plurality of pillars are disposed on the semiconductor package. The lid is disposed on the substrate and covers the semiconductor package and the plurality of pillars. The lid includes an inflow channel and an outflow channel to allow a coolant to flow into and out of a space between the substrate, the semiconductor package, the plurality of pillars and the lid. An inner surface of the lid, which faces and overlaps the plurality of pillars along a stacking direction of the semiconductor package and the lid, is a flat surface.

    PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
    4.
    发明申请
    PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME 审中-公开

    公开(公告)号：US20190115311A1

    公开(公告)日：2019-04-18

    申请号：US16219981

    申请日：2018-12-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

    IPC: H01L23/00 ,  H01L23/31

    Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, and an RDL structure. The encapsulant is laterally encapsulating the die. The RDL structure is electrically connected to the die. The RDL structure includes a first dielectric layer, a first RDL, a second dielectric layer and a second RDL. The first dielectric layer is disposed on the encapsulant and the die. The first RDL is embedded in the first dielectric layer. The first RDL includes a first via and a first trace connected to each other. A top surface of the first RDL is coplanar with a top surface of the first dielectric layer. The second dielectric layer is on the first dielectric layer and the first RDL. The second RDL is embedded in the second dielectric layer and includes a second via and a second trace connected to each other. A top surface of the second RDL is coplanar with a top surface of the second dielectric layer. The second via is stacked directly on the first via.

    Semiconductor device and manufacturing method thereof
    5.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US11139223B2

    公开(公告)日：2021-10-05

    申请号：US16655257

    申请日：2019-10-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Jeng-Nan Hung ,  Kuo-Chung Yee

    IPC: H01L23/34 ,  H01L23/473 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31 ,  H01L21/50 ,  H01L21/308

    Abstract: A semiconductor package includes a semiconductor package, a cap, a seal, and microstructures. The semiconductor package includes at least one semiconductor die. The cap is disposed over an upper surface of the semiconductor package. The seal is located on the semiconductor package and between the cap and the semiconductor package. The cap includes an inflow channel and an outflow channel. The active surface of the at least one semiconductor die faces away from the cap. The cap and an upper surface of the semiconductor package define a circulation recess providing fluidic communication between the inflow channel and the outflow channel. The seal is disposed around the circulation recess. The microstructures are located within the circulation recess, and the microstructures are connected to at least one of the cap and the at least one semiconductor die.

    Semiconductor structure comprising at least one system-on-integrated-circuit component
    9.
    发明授权
    Semiconductor structure comprising at least one system-on-integrated-circuit component 有权

    公开(公告)号：US11380645B2

    公开(公告)日：2022-07-05

    申请号：US16935175

    申请日：2020-07-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Jeng-Nan Hung ,  Kuo-Chung Yee ,  Po-Fan Lin

    IPC: H01L23/00 ,  H01L23/48

    Abstract: A structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The first bonding structure includes a first dielectric layer and first conductors embedded in the first dielectric layer. The second semiconductor die includes a second bonding structure. The second bonding structure includes a second dielectric layer and second conductors embedded in the second dielectric layer. The first dielectric layer is in contact with the second dielectric layer, and the first conductors are in contact with the second conductors. Thermal conductivity of the first dielectric layer and the second dielectric layer is greater than thermal conductivity of silicon dioxide.

    Package structure and method of forming the same
    10.
    发明授权
    Package structure and method of forming the same 有权

    公开(公告)号：US11069636B2

    公开(公告)日：2021-07-20

    申请号：US16714814

    申请日：2019-12-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

    IPC: H01L23/52 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

    Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a first polymer material layer, a second polymer material layer and a first redistribution layer. The encapsulant encapsulates sidewalls of the die. The first polymer material layer is on the encapsulant and the die. The second polymer material layer is on the first polymer material layer. The first redistribution layer is embedded in the first polymer material layer and the second polymer material layer and electrically connected to the die. The first redistribution layer has a top surface substantially coplanar with a top surface of the second polymer material layer, and a portion of a top surface of the first polymer material layer is in contact with the first redistribution layer.

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