Invention Grant
- Patent Title: Method to embed planar FETs with finFETs
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Application No.: US16858801Application Date: 2020-04-27
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Publication No.: US11355493B2Publication Date: 2022-06-07
- Inventor: Harry-Hak-Lay Chuang , Wei Cheng Wu , Li-Feng Teng , Li-Jung Liu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L29/417 ; H01L29/06

Abstract:
Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.
Public/Granted literature
- US20210288048A1 METHOD TO EMBED PLANAR FETS WITH FINFETS Public/Granted day:2021-09-16
Information query
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