公开(公告)号：US11825651B2

公开(公告)日：2023-11-21

申请号：US17135744

申请日：2020-12-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Cheng Wu ,  Li-Feng Teng

IPC: H01L29/423 ,  H10B41/42 ,  H10B41/35 ,  H01L21/28 ,  H10B41/30 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48 ,  H10B43/30 ,  H01L29/66

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66545 ,  H10B41/30 ,  H10B41/35 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48 ,  H10B43/30

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

公开(公告)号：US11430799B2

公开(公告)日：2022-08-30

申请号：US16588090

申请日：2019-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Chin Liu ,  Wei Cheng Wu ,  Yi Hsien Lu ,  Yu-Hsiung Wang ,  Juo-Li Yang

IPC: H01L27/11 ,  H01L27/11546 ,  H01L27/088 ,  H01L29/788 ,  H01L21/28 ,  H01L27/105 ,  G11C16/12 ,  G11C16/04 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/11548 ,  H01L29/423

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

公开(公告)号：US11355493B2

公开(公告)日：2022-06-07

申请号：US16858801

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Li-Feng Teng ,  Li-Jung Liu

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/06

Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

公开(公告)号：US11348935B2

公开(公告)日：2022-05-31

申请号：US16869780

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L27/11568 ,  H01L29/792 ,  H01L29/423 ,  H01L21/311 ,  H01L29/66

Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

公开(公告)号：US11264402B2

公开(公告)日：2022-03-01

申请号：US16695505

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L27/11575 ,  H01L29/06 ,  H01L21/76 ,  H01L27/11573 ,  H01L21/762

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of memory devices within an embedded memory region of a substrate and forming a plurality of transistor devices within a logic region of the substrate. A first isolation structure is formed within a boundary region of the substrate disposed between the logic region and the embedded memory region. The first isolation structure is formed within a recess in the substrate. A logic wall is formed over the first isolation structure. The logic wall surrounds the embedded memory region and has a first height that is greater than heights of the plurality of memory devices.

公开(公告)号：US11069419B2

公开(公告)日：2021-07-20

申请号：US16122104

申请日：2018-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Tsung Lien ,  Fang-Lan Chu ,  Hong-Da Lin ,  Wei Cheng Wu ,  Ku-Ning Chang ,  Yu-Chen Wang

IPC: H01L29/788 ,  G11C29/02 ,  H01L21/28 ,  G01R31/28 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L27/11526 ,  H01L27/11573 ,  G11C29/56 ,  H01L21/66

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a test line letter structure having one or more sidewalls continuously extending along a path that defines a shape of an alpha-numeric character from a top-view. The test line letter structure is formed by forming a first polysilicon structure over a substrate and forming a second polysilicon structure over the substrate at a location laterally separated from first polysilicon structure by a dielectric layer.

公开(公告)号：US11056566B2

公开(公告)日：2021-07-06

申请号：US16705508

申请日：2019-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L29/423 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/66 ,  H01L29/51

Abstract: The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a sacrificial spacer over a substrate and forming a select gate along a side of the sacrificial spacer. An inter-gate dielectric is formed over the select gate and the sacrificial spacer. A memory gate layer is formed over the inter-gate dielectric and the sacrificial spacer. The memory gate layer is laterally separated from the sacrificial spacer by the select gate. The memory gate layer is etched to define a memory gate having a topmost point below a top of the sacrificial spacer.

公开(公告)号：US10950715B2

公开(公告)日：2021-03-16

申请号：US16203352

申请日：2018-11-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Cheng Wu ,  Li-Feng Teng

IPC: H01L29/66 ,  H01L21/28 ,  H01L27/11546 ,  H01L21/762 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/11548 ,  H01L29/06 ,  H01L29/423 ,  H01L29/788

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate and having one of a silicon oxide layer, a silicon nitride layer and multilayers of silicon oxide and silicon nitride, and an erase gate and a select gate. The erase gate and the select gate include a stack of a bottom polysilicon layer and an upper metal layer.

公开(公告)号：US10784270B2

公开(公告)日：2020-09-22

申请号：US16051721

申请日：2018-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/11536 ,  H01L29/788 ,  H01L29/423 ,  H01L29/49 ,  H01L29/08 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/027 ,  H01L27/11521

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A sidewall spacer is disposed along a sidewall surface of the logic devices, but not disposed along a sidewall surface of the memory cell structures. Thus, the inter-layer dielectric (ILD) fill-in window between adjacent memory cell structures is enlarged, compared to the approaches where the sidewall spacer is concurrently formed in both memory region and the logic region. Thereby, voids formation would be reduced or eliminated, and device quality would be improved.

公开(公告)号：US10665595B2

公开(公告)日：2020-05-26

申请号：US15903770

申请日：2018-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Hsin Chiu ,  Meng-Han Lin ,  Wei Cheng Wu

IPC: G06F17/50 ,  H01L27/11 ,  H01L23/528 ,  G11C29/50 ,  G11C29/08 ,  G11C29/04 ,  G11C29/12 ,  G06F30/39 ,  G06F30/398

Abstract: In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC.