- 专利标题: Memory with optimized resistive layers
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申请号: US16941885申请日: 2020-07-29
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公开(公告)号: US11380732B2公开(公告)日: 2022-07-05
- 发明人: Lei Wei , Pengyuan Zheng , Kevin Lee Baker , Efe Sinan Ege , Adam Thomas Barton , Rajasekhar Venigalla
- 申请人: Micron Technology, Inc.
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 代理机构: Holland & Hart LLP
- 主分类号: H01L27/24
- IPC分类号: H01L27/24 ; H01L45/00
摘要:
A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.
公开/授权文献
- US20220037403A1 MEMORY WITH OPTIMIZED RESISTIVE LAYERS 公开/授权日:2022-02-03
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