公开(公告)号：US20220406847A1

公开(公告)日：2022-12-22

申请号：US17846731

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Lei Wei ,  Pengyuan Zheng ,  Kevin Lee Baker ,  Efe Sinan Ege ,  Adam Thomas Barton ,  Rajasekhar Venigalla

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.

公开(公告)号：US11830816B2

公开(公告)日：2023-11-28

申请号：US16993695

申请日：2020-08-14

Applicant: Micron Technology, Inc.

Inventor： Lei Wei ,  Adam Thomas Barton

IPC: H01L23/538 ,  G11C5/06 ,  H01L21/768 ,  G11C7/10

CPC classification number: H01L23/5384 ,  G11C5/06 ,  G11C7/1078 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5386

Abstract: Methods, systems, and devices for reduced resistivity for access lines in a memory array are described. A first metal layer may be formed above a via that is configured to couple an access line of a memory array with a corresponding driver. The first metal layer may be oxidized, and then a second metal layer may be formed above the oxidized first metal layer. One or more access lines of the memory device may be formed from the second metal layer, the oxidized first metal layer, or both.

公开(公告)号：US20240162156A1

公开(公告)日：2024-05-16

申请号：US18513303

申请日：2023-11-17

Applicant: Micron Technology, Inc.

Inventor： Lei Wei ,  Adam Thomas Barton

IPC: H01L23/538 ,  G11C5/06 ,  G11C7/10 ,  H01L21/768

CPC classification number: H01L23/5384 ,  G11C5/06 ,  G11C7/1078 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5386

Abstract: Methods, systems, and devices for reduced resistivity for access lines in a memory array are described. A first metal layer may be formed above a via that is configured to couple an access line of a memory array with a corresponding driver. The first metal layer may be oxidized, and then a second metal layer may be formed above the oxidized first metal layer. One or more access lines of the memory device may be formed from the second metal layer, the oxidized first metal layer, or both.

公开(公告)号：US11778837B2

公开(公告)日：2023-10-03

申请号：US17846731

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Lei Wei ,  Pengyuan Zheng ,  Kevin Lee Baker ,  Efe Sinan Ege ,  Adam Thomas Barton ,  Rajasekhar Venigalla

IPC: H01L27/24 ,  H01L45/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/84 ,  H10N70/063 ,  H10N70/231 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8616

Abstract: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.

公开(公告)号：US11380732B2

公开(公告)日：2022-07-05

申请号：US16941885

申请日：2020-07-29

Applicant: Micron Technology, Inc.

Inventor： Lei Wei ,  Pengyuan Zheng ,  Kevin Lee Baker ,  Efe Sinan Ege ,  Adam Thomas Barton ,  Rajasekhar Venigalla

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.

公开(公告)号：US20220037403A1

公开(公告)日：2022-02-03

申请号：US16941885

申请日：2020-07-29

Applicant: Micron Technology, Inc.

Inventor： Lei Wei ,  Pengyuan Zheng ,  Kevin Lee Baker ,  Efe Sinan Ege ,  Adam Thomas Barton ,  Rajasekhar Venigalla

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.