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公开(公告)号：US12082425B2
公开(公告)日：2024-09-03
申请号：US18124438
申请日：2023-03-21
发明人： Don Koun Lee , Kevin Lee Baker , Lei Wei
CPC分类号： H10B63/84 , H10N70/063 , H10N70/231 , H10N70/826 , H10N70/841 , H10N70/882
摘要： Methods, systems, and devices for efficient fabrication of memory structures are described. A multi-deck memory device may be fabricated using a sequence of fabrication steps that include depositing a first metal layer, depositing a cell layer on the first metal layer to form memory cells of the first memory deck, and depositing a second metal layer on the cell layer. The second metal layer may be deposited using a single deposition process rather than using multiple deposition processes. A second memory deck may be formed on the second metal layer such that stacked memory cells from the first and second deck share the use of the second metal layer. Using a single deposition process for the second metal layer may decrease the quantity of fabrication steps used to fabricate the multi-deck memory array and reduce or eliminate the exposure of the cell material to metal etchants.
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公开(公告)号：US11626452B2
公开(公告)日：2023-04-11
申请号：US16940774
申请日：2020-07-28
发明人： Don Koun Lee , Kevin Lee Baker , Lei Wei
摘要： Methods, systems, and devices for efficient fabrication of memory structures are described. A multi-deck memory device may be fabricated using a sequence of fabrication steps that include depositing a first metal layer, depositing a cell layer on the first metal layer to form memory cells of the first memory deck, and depositing a second metal layer on the cell layer. The second metal layer may be deposited using a single deposition process rather than using multiple deposition processes. A second memory deck may be formed on the second metal layer such that stacked memory cells from the first and second deck share the use of the second metal layer. Using a single deposition process for the second metal layer may decrease the quantity of fabrication steps used to fabricate the multi-deck memory array and reduce or eliminate the exposure of the cell material to metal etchants.
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公开(公告)号：US11778837B2
公开(公告)日：2023-10-03
申请号：US17846731
申请日：2022-06-22
发明人： Lei Wei , Pengyuan Zheng , Kevin Lee Baker , Efe Sinan Ege , Adam Thomas Barton , Rajasekhar Venigalla
CPC分类号： H10B63/84 , H10N70/063 , H10N70/231 , H10N70/826 , H10N70/841 , H10N70/8616
摘要： A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.
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公开(公告)号：US20220037402A1
公开(公告)日：2022-02-03
申请号：US16940774
申请日：2020-07-28
发明人： Don Koun Lee , Kevin Lee Baker , Lei Wei
摘要： Methods, systems, and devices for efficient fabrication of memory structures are described. A multi-deck memory device may be fabricated using a sequence of fabrication steps that include depositing a first metal layer, depositing a cell layer on the first metal layer to form memory cells of the first memory deck, and depositing a second metal layer on the cell layer. The second metal layer may be deposited using a single deposition process rather than using multiple deposition processes. A second memory deck may be formed on the second metal layer such that stacked memory cells from the first and second deck share the use of the second metal layer. Using a single deposition process for the second metal layer may decrease the quantity of fabrication steps used to fabricate the multi-deck memory array and reduce or eliminate the exposure of the cell material to metal etchants.
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公开(公告)号：US20230225137A1
公开(公告)日：2023-07-13
申请号：US18124438
申请日：2023-03-21
发明人： Don Koun Lee , Kevin Lee Baker , Lei Wei
IPC分类号： H01L47/00
CPC分类号： H10B63/84 , H10N70/231 , H10N70/882 , H10N70/826 , H10N70/841 , H10N70/063
摘要： Methods, systems, and devices for efficient fabrication of memory structures are described. A multi-deck memory device may be fabricated using a sequence of fabrication steps that include depositing a first metal layer, depositing a cell layer on the first metal layer to form memory cells of the first memory deck, and depositing a second metal layer on the cell layer. The second metal layer may be deposited using a single deposition process rather than using multiple deposition processes. A second memory deck may be formed on the second metal layer such that stacked memory cells from the first and second deck share the use of the second metal layer. Using a single deposition process for the second metal layer may decrease the quantity of fabrication steps used to fabricate the multi-deck memory array and reduce or eliminate the exposure of the cell material to metal etchants.
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公开(公告)号：US11380732B2
公开(公告)日：2022-07-05
申请号：US16941885
申请日：2020-07-29
发明人： Lei Wei , Pengyuan Zheng , Kevin Lee Baker , Efe Sinan Ege , Adam Thomas Barton , Rajasekhar Venigalla
摘要： A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.
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公开(公告)号：US20220037403A1
公开(公告)日：2022-02-03
申请号：US16941885
申请日：2020-07-29
发明人： Lei Wei , Pengyuan Zheng , Kevin Lee Baker , Efe Sinan Ege , Adam Thomas Barton , Rajasekhar Venigalla
摘要： A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.
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公开(公告)号：US20240224825A1
公开(公告)日：2024-07-04
申请号：US18409413
申请日：2024-01-10
发明人： Rajasekhar Venigalla , Patrick M. Flynn , Josiah Jebaraj Johnley Muthuraj , Efe Sinan Ege , Kevin Lee Baker , Tao Nguyen , Davis Weymann
IPC分类号： H10N70/00 , G11C13/00 , H01L21/768 , H01L23/522 , H01L23/528 , H10B63/00 , H10N70/20
CPC分类号： H10N70/8616 , G11C13/0004 , H01L21/76802 , H01L21/76831 , H01L21/76834 , H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L23/528 , H10B63/84 , H10N70/021 , H10N70/231 , H10N70/826 , H10N70/841 , G11C13/004 , G11C2013/005 , G11C13/0069 , G11C2013/0078 , G11C2213/52 , G11C2213/71 , H10N70/8825
摘要： Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.
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公开(公告)号：US11882774B2
公开(公告)日：2024-01-23
申请号：US17468167
申请日：2021-09-07
发明人： Rajasekhar Venigalla , Patrick M. Flynn , Josiah Jebaraj Johnley Muthuraj , Efe Sinan Ege , Kevin Lee Baker , Tao Nguyen , Davis Weymann
IPC分类号： H10N70/00 , H01L21/768 , H01L23/522 , G11C13/00 , H01L23/528 , H10B63/00 , H10N70/20
CPC分类号： H10N70/8616 , G11C13/0004 , H01L21/76802 , H01L21/76831 , H01L21/76834 , H01L21/76843 , H01L21/76877 , H01L23/528 , H01L23/5226 , H10B63/84 , H10N70/021 , H10N70/231 , H10N70/826 , H10N70/841 , G11C13/004 , G11C13/0069 , G11C2013/005 , G11C2013/0078 , G11C2213/52 , G11C2213/71 , H10N70/8825
摘要： Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.
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公开(公告)号：US20220406847A1
公开(公告)日：2022-12-22
申请号：US17846731
申请日：2022-06-22
发明人： Lei Wei , Pengyuan Zheng , Kevin Lee Baker , Efe Sinan Ege , Adam Thomas Barton , Rajasekhar Venigalla
摘要： A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.
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