- 专利标题: Controlling timing and ramp rate of program-inhibit voltage signal during programming to optimize peak current
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申请号: US16778821申请日: 2020-01-31
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公开(公告)号: US11417400B2公开(公告)日: 2022-08-16
- 发明人: Yu-Chung Lien , Huai-Yuan Tseng , Deepanshu Dutta
- 申请人: SanDisk Technologies LLC
- 申请人地址: US TX Addison
- 专利权人: SanDisk Technologies LLC
- 当前专利权人: SanDisk Technologies LLC
- 当前专利权人地址: US TX Addison
- 代理机构: Vierra Magen Marcus LLP
- 主分类号: G11C16/00
- IPC分类号: G11C16/00 ; G11C16/26 ; H01L27/11556 ; G11C5/06 ; G11C16/10 ; G11C5/02 ; H01L27/11582
摘要:
Techniques are described for optimizing the peak current during a program operation by controlling a timing and ramp rate of a program-inhibit voltage signal as a function of a program loop number and/or program progress. A transition voltage between a regulated ramp up rate and an unregulated ramp up rate can also be adjusted. For initial and final sets of program loops in a program operation, the ramp up of the program-inhibit voltage signal can occur early so that it overlaps with operations of sense circuits in updating their latches based on results from a verify test in a previous program loop. For an intermediate set of program loops, the overlap is avoided. The ramp up rate can be larger and the transition voltage smaller for the initial and final sets of program loops compared to the intermediate set of program loops.
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