Invention Grant
- Patent Title: Voltage equalization for pillars of a memory array
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Application No.: US17116893Application Date: 2020-12-09
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Publication No.: US11437097B2Publication Date: 2022-09-06
- Inventor: Corrado Villa , Ferdinando Bedeschi , Paolo Fantini
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G11C13/00
- IPC: G11C13/00 ; H01L45/00

Abstract:
Methods, systems, and devices for voltage equalization for pillars of a memory array are described. In some examples, a memory array may be configured with conductive pillars that are each coupled with a respective set of memory cells, and may be selectively coupled with an access line. To support a dissipation or equalization of charge from unselected pillars, the memory array may be configured with a material layer or level that provides a dissipative coupling, such as a coupling having a relatively high resistance or a degree of capacitance, with a ground voltage or other voltage source (e.g., to support a passive equalization). Additionally or alternatively, a memory array may be configured to support an active dissipation of accumulated charge or voltage by selectively coupling pillars that have been operated in a floating condition with a ground voltage or other voltage source (e.g., to perform a dynamic equalization).
Public/Granted literature
- US20220180926A1 VOLTAGE EQUALIZATION FOR PILLARS OF A MEMORY ARRAY Public/Granted day:2022-06-09
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