公开(公告)号：US20240237358A1

公开(公告)日：2024-07-11

申请号：US18407074

申请日：2024-01-08

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Corrado Villa ,  Stefan Frederik Schippers ,  Efrem Bolandrina

IPC: H10B63/00 ,  G11C13/00

CPC classification number: H10B63/34 ,  G11C13/0004 ,  G11C13/003 ,  H10B63/845 ,  G11C2213/71 ,  G11C2213/79

Abstract: The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.

公开(公告)号：US11887664B2

公开(公告)日：2024-01-30

申请号：US18079515

申请日：2022-12-12

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Corrado Villa

IPC: G11C7/14 ,  G11C16/28 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2013/0045

Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage to the memory array based on the read request. The control circuit is additionally configured to count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage and to apply a second voltage to the memory array based on the total number. The control circuit is further configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.

公开(公告)号：US11877457B2

公开(公告)日：2024-01-16

申请号：US16976411

申请日：2020-05-25

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Corrado Villa ,  Stefan Frederik Schippers ,  Efrem Bolandrina

IPC: G11C11/00 ,  H10B63/00 ,  G11C13/00

CPC classification number: H10B63/34 ,  G11C13/003 ,  G11C13/0004 ,  H10B63/845 ,  G11C2213/71 ,  G11C2213/79

Abstract: The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.

公开(公告)号：US11244713B2

公开(公告)日：2022-02-08

申请号：US16748671

申请日：2020-01-21

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa

IPC: G11C8/16 ,  G11C7/10 ,  G11C7/04 ,  G11C29/18 ,  G11C8/10

Abstract: Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.

公开(公告)号：US20210335436A1

公开(公告)日：2021-10-28

申请号：US17236729

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Shane D. Moser

IPC: G11C29/18 ,  G11C11/419 ,  G11C11/408 ,  G11C11/22 ,  G11C13/00 ,  G11C16/04

Abstract: Methods, systems, and devices for word line capacitance balancing are described. A memory device may include a set of memory tiles, where one or more memory tiles may be located at a boundary of the set. Each boundary memory tile may have a word line coupled with a driver and a subarray of memory cells, and may also include a load balancing component (e.g., a capacitive component) coupled with the driver. In some examples, the load balancing component may be coupled with an output line of the driver (such as a word line) or an input of the driver (such as a line providing a source signal). The load balancing component may adapt a load output from the driver to the subarray of memory cells such that the load of the memory tile at the boundary may be similar to the load of other memory tiles not at the boundary.

公开(公告)号：US20210027852A1

公开(公告)日：2021-01-28

申请号：US16518824

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Shane D. Moser

IPC: G11C29/18 ,  G11C11/408 ,  G11C11/419

Abstract: Methods, systems, and devices for word line capacitance balancing are described. A memory device may include a set of memory tiles, where one or more memory tiles may be located at a boundary of the set. Each boundary memory tile may have a word line coupled with a driver and a subarray of memory cells, and may also include a load balancing component (e.g., a capacitive component) coupled with the driver. In some examples, the load balancing component may be coupled with an output line of the driver (such as a word line) or an input of the driver (such as a line providing a source signal). The load balancing component may adapt a load output from the driver to the subarray of memory cells such that the load of the memory tile at the boundary may be similar to the load of other memory tiles not at the boundary.

公开(公告)号：US20210012827A1

公开(公告)日：2021-01-14

申请号：US16509916

申请日：2019-07-12

Applicant: Micron Technology, Inc.

Inventor： Stefan Frederik Schippers ,  Christophe Vincent Antoine Laurent ,  Corrado Villa

IPC: G11C11/4074 ,  G06F1/3296 ,  G11C11/406

Abstract: Methods, systems, and devices for power domain switches for switching power reduction are described. A device, such as a memory device, may receive an indication (e.g., a command) for a power domain component of the device to transition between states. The device may float first and second gate drivers. A pass gate may be used to connect (e.g., short) the first switch to the second switch. The pass gate may be deactivated to isolate the gates. The first and second gate drivers may be enabled, and the first and second gate drivers drive the first and second switches to disconnect the power domain component from a power source to deactivate the power domain component, or connect to the power source to activate the power domain component. The energy to switch between active and inactive states may thereby be reduced.

公开(公告)号：US20200058341A1

公开(公告)日：2020-02-20

申请号：US16104693

申请日：2018-08-17

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Andrea Martinelli

IPC: G11C11/22 ,  G06F3/06

Abstract: Methods, systems, and devices for activity-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include determining a quantity of access operations performed on a set of sections of a memory device, selecting at least one of the sections for a voltage adjustment operation based on the determined quantity of access operations, and performing the voltage adjustment operation on the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.

公开(公告)号：US10566040B2

公开(公告)日：2020-02-18

申请号：US15223753

申请日：2016-07-29

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa

IPC: G11C8/16 ,  G11C7/10 ,  G11C7/04 ,  G11C29/18 ,  G11C8/10

Abstract: Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.

公开(公告)号：US20200035287A1

公开(公告)日：2020-01-30

申请号：US16536141

申请日：2019-08-08

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Corrado Villa

IPC: G11C11/22 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. An electronic memory device may include a plurality of plate portions separated by a plurality of segmentation lines, which may be oriented in a plane parallel to rows of a memory array or columns of the memory array, or both. The segmented plate may be employed instead of a single plate for the array. The one or more plate portions may be energized during access operations of a ferroelectric cell in order to create a voltage different across the cell or to facilitate changing the charge of the cell. Each of the plate portions may include one or more memory cells. The memory cells on a plate portion may be read from or written to after the plate portion is activated by a plate driver.