Invention Grant
- Patent Title: Data bus duty cycle distortion compensation
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Application No.: US16949510Application Date: 2020-10-30
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Publication No.: US11442877B2Publication Date: 2022-09-13
- Inventor: Guan Wang , Ali Feiz Zarrin Ghalam , Chin-Yu Chen , Jongin Kim
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F13/36
- IPC: G06F13/36 ; G06F13/16 ; H03K3/017 ; G11C16/32 ; G11C16/04

Abstract:
An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.
Public/Granted literature
- US20220138120A1 DATA BUS DUTY CYCLE DISTORTION COMPENSATION Public/Granted day:2022-05-05
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