Invention Grant
- Patent Title: Synapse circuit with memory
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Application No.: US16719761Application Date: 2019-12-18
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Publication No.: US11449740B2Publication Date: 2022-09-20
- Inventor: Bharani Chakravarthy Chava , Shairfe Muhammad Salahuddin , Hyungrock Oh
- Applicant: IMEC vzw
- Applicant Address: BE Leuven
- Assignee: IMEC vzw
- Current Assignee: IMEC vzw
- Current Assignee Address: BE Leuven
- Agency: Knobbe Martens Olson & Bear, LLP
- Priority: EP18215290 20181221
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C7/18 ; G06N3/04 ; G06N3/063 ; G06N3/08 ; G11C11/54

Abstract:
A synapse circuit with an arrayed structured memory for machine learning applications is disclosed. The synapse circuit comprises a controlled variable resistance, a controlled switch connected to a contact terminal of the controlled variable resistance, and a memory cell for storing a weight variable. The memory cell is operatively connected to a control terminal of the controlled switch. A control terminal of the controlled variable resistance is configured for receiving an activation signal. The controlled variable resistance has a first resistance value and a second resistance value substantially larger than the first resistance value. A ratio of the second resistance value to the first resistance value is at least one hundred. A current, flowing through the controlled switch and the controlled variable resistance, (1) is indicative of the activation signal weighted by the stored weight variable if the controlled variable resistance is the first resistance value and (2) is smaller or equal to one picoampere at room temperature if the controlled variable resistance is adopting the second resistance value.
Information query