公开(公告)号：US20230413505A1

公开(公告)日：2023-12-21

申请号：US18335320

申请日：2023-06-15

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Hsiao-Hsuan Liu ,  Shairfe Muhammad Salahuddin ,  Boon Teik Chan

IPC: H10B10/00

CPC classification number: H10B10/125

Abstract: A bit cell for a Static Random-Access Memory (SRAM) is provided that includes a first and second pair of complementary transistors as well as a first pass-gate transistor and a second pass-gate transistor. A first inverter gate electrode forms a common gate electrode for the first pair of complementary transistors and a second inverter gate electrode forms a common gate electrode for the second pair of complementary transistors. Further, a first pass gate electrode forms a gate of the first pass-gate transistor and a second pass gate electrode forms a gate of the second pass-gate transistor. A first and a second dielectric wall are also provided, separating the first pass gate electrode from the first inverter gate electrode, and the second pass gate electrode from the second inverter gate electrode.

公开(公告)号：US11251036B2

公开(公告)日：2022-02-15

申请号：US16719725

申请日：2019-12-18

Applicant: IMEC vzw

Inventor： Shairfe Muhammad Salahuddin ,  Alessio Spessot

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66

Abstract: The disclosed technology generally relates to semiconductor devices and methods of manufacturing semiconductor devices such as both logic and memory semiconductor devices. In one aspect, a semiconductor device includes a semiconductor substrate having a channel region between a source and a drain region, a gate structure arranged to control the channel region and a dielectric structure arranged between the channel region and the gate structure. The dielectric structure includes a high-k dielectric layer or a high-k ferroelectric layer and at least one two dimensional (2D) hexagonal boron-nitride (h-BN) layer in direct contact with the high-k dielectric layer or the high-k ferroelectric layer.

公开(公告)号：US20190198080A1

公开(公告)日：2019-06-27

申请号：US16196335

申请日：2018-11-20

Applicant: IMEC vzw

Inventor： Shairfe Muhammad Salahuddin ,  Alessio Spessot ,  Jan Van Houdt ,  Julien Ryckaert

IPC: G11C11/22 ,  H01L27/11585 ,  H01L29/78 ,  H01L29/51

CPC classification number: G11C11/223 ,  G11C11/2275 ,  H01L21/28291 ,  H01L27/11585 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

Abstract: According to one aspect, a ferroelectric field effect transistor (FeFET) memory device and a method of programming the device is disclosed. The FeFET is configured such that a ferroelectric memory region of the FeFET is programmable by an electric field applied between a gate structure and a source region and a drain region through the ferroelectric region.

公开(公告)号：US11449740B2

公开(公告)日：2022-09-20

申请号：US16719761

申请日：2019-12-18

Applicant: IMEC vzw

Inventor： Bharani Chakravarthy Chava ,  Shairfe Muhammad Salahuddin ,  Hyungrock Oh

IPC: G11C7/10 ,  G11C7/18 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G11C11/54

Abstract: A synapse circuit with an arrayed structured memory for machine learning applications is disclosed. The synapse circuit comprises a controlled variable resistance, a controlled switch connected to a contact terminal of the controlled variable resistance, and a memory cell for storing a weight variable. The memory cell is operatively connected to a control terminal of the controlled switch. A control terminal of the controlled variable resistance is configured for receiving an activation signal. The controlled variable resistance has a first resistance value and a second resistance value substantially larger than the first resistance value. A ratio of the second resistance value to the first resistance value is at least one hundred. A current, flowing through the controlled switch and the controlled variable resistance, (1) is indicative of the activation signal weighted by the stored weight variable if the controlled variable resistance is the first resistance value and (2) is smaller or equal to one picoampere at room temperature if the controlled variable resistance is adopting the second resistance value.

公开(公告)号：US11276606B2

公开(公告)日：2022-03-15

申请号：US16577332

申请日：2019-09-20

Applicant: IMEC VZW

Inventor： Shairfe Muhammad Salahuddin ,  Alessio Spessot

IPC: H01L21/764 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51

Abstract: A method for forming airgaps within an integrated electronic circuit implements a conformal layer and a nanosheet both of boron nitride. The method has advantages for the circuit due to special properties of boron nitride material. In particular, mechanical strength and heat dissipation are increased whereas electro-migration is limited. The method may be applied to the first interconnect layer of the integrated circuit, for reducing additionally capacitive interactions existing between gate electrode structures and source or drain contact structures.

公开(公告)号：US20200211839A1

公开(公告)日：2020-07-02

申请号：US16719725

申请日：2019-12-18

Applicant: IMEC vzw

Inventor： Shairfe Muhammad Salahuddin ,  Alessio Spessot

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/10

Abstract: The disclosed technology generally relates to semiconductor devices and methods of manufacturing semiconductor devices such as both logic and memory semiconductor devices. In one aspect, a semiconductor device includes a semiconductor substrate having a channel region between a source and a drain region, a gate structure arranged to control the channel region and a dielectric structure arranged between the channel region and the gate structure. The dielectric structure includes a high-k dielectric layer or a high-k ferroelectric layer and at least one two dimensional (2D) hexagonal boron-nitride (h-BN) layer in direct contact with the high-k dielectric layer or the high-k ferroelectric layer.

公开(公告)号：US20240206145A1

公开(公告)日：2024-06-20

申请号：US18545760

申请日：2023-12-19

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Hsiao-Hsuan Liu ,  Shairfe Muhammad Salahuddin ,  Boon Teik Chan ,  Sujith Subramanian

IPC: H10B10/00 ,  H01L23/528

CPC classification number: H10B10/125 ,  H01L23/5286

Abstract: The present disclosure relates to static random access memory (SRAM). In particular, the disclosure provides a stacked SRAM cell, and a method for fabricating the stacked SRAM cell. The stacked SRAM cell comprises two first transistor structures and two second transistor structures, which form a pair of cross-coupled inverters, an comprises one or two pass gate (PG) transistor structures. Further, the stacked SRAM cell comprises a first power rail and/or a second power rail arranged above the transistor structures, wherein the first power rail is connected by respective first vias to the first transistor structures from above, and/or the second power rail is connected by respective second vias to the second transistor structures from above. The SRAM cell also comprises one or two bit lines arranged below the PG transistor structures. Each bit line is connected by a respective third via to one PG transistor structure from below.

公开(公告)号：US20230413504A1

公开(公告)日：2023-12-21

申请号：US18335310

申请日：2023-06-15

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Hsiao-Hsuan Liu ,  Shairfe Muhammad Salahuddin ,  Boon Teik Chan

IPC: H10B10/00

CPC classification number: H10B10/125

Abstract: A bit cell for a Static Random-Access Memory (SRAM) is provided that includes first and second sets of transistors. Each set of transistors includes a respective pass-gate transistor and a respectively stacked complementary transistor pair of an upper transistor and a lower transistor. A source/drain terminal of a lower transistor of each set of transistors is connected to a respective first power supply extending in a first power supply track arranged below the lower transistor, whereas a source/drain terminal of an upper transistor of each set of transistors is connected to a respective second power supply extending in a second power supply track arranged above the upper transistor.

公开(公告)号：US20230206996A1

公开(公告)日：2023-06-29

申请号：US18068330

申请日：2022-12-19

Applicant: IMEC VZW

Inventor： Shairfe Muhammad Salahuddin ,  Julien Ryckaert

IPC: G11C11/419 ,  H01L23/522 ,  H01L23/528 ,  H10B80/00 ,  H10B10/00 ,  H01L25/16

CPC classification number: G11C11/419 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/16 ,  H10B10/12 ,  H10B80/00

Abstract: A multiport memory cell for register files is disclosed. Vertically stacked top and bottom tier of the memory cell are electrically interconnected through a pair of vias and comprise each an active device layer and a metal layer stack. The memory cell is partitioned to have a latching circuit and at least one write port located in the bottom tier and at least two read ports in the top tier. A word line trace for controlling the at least one write port is formed in the bottom tier metal layer stack and comprises two terminal sections and one intermediate section oriented perpendicularly to the terminal sections. The intermediate section is arranged between the pair of vias in a height direction of the memory cell.

公开(公告)号：US20200083234A1

公开(公告)日：2020-03-12

申请号：US16565112

申请日：2019-09-09

Applicant: IMEC vzw

Inventor： Shairfe Muhammad Salahuddin ,  Jan Van Houdt ,  Julien Ryckaert ,  Alessio Spessot

IPC: H01L27/1159 ,  H01L27/108 ,  G11C11/4096 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/11592

Abstract: The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.