公开(公告)号：US11645503B2

公开(公告)日：2023-05-09

申请号：US16723131

申请日：2019-12-20

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Mohit Gupta ,  Bharani Chakravarthy Chava ,  Wim Dehaene ,  Sushil Sakhare

IPC: G06N3/063 ,  G06F7/544 ,  G06N3/04 ,  G11C11/54

CPC classification number: G06N3/063 ,  G06F7/5443 ,  G06N3/04 ,  G11C11/54

Abstract: A circuit is provided. The circuit includes a sampling circuit connectable to a multibit memory array and that samples a voltage across a sampling capacitor, a capacitance network including a plurality of capacitors and switching elements such that the capacitance network has a capacitance that depends on the configuration of the switching elements, and a buffering circuit configured to charge the capacitance of the capacitance network based on the voltage across the sampling capacitor. The circuit is configured to operate the capacitance network in a first state and a second state, wherein the capacitance in the states depends on an input value to the circuit. The circuit is also configured to charge the capacitance network in the first state and to allow the charge to redistribute within the capacitance network when it changes from the first to the second state. A system and method including such circuits are also provided.

公开(公告)号：US11449740B2

公开(公告)日：2022-09-20

申请号：US16719761

申请日：2019-12-18

Applicant: IMEC vzw

Inventor： Bharani Chakravarthy Chava ,  Shairfe Muhammad Salahuddin ,  Hyungrock Oh

IPC: G11C7/10 ,  G11C7/18 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G11C11/54

Abstract: A synapse circuit with an arrayed structured memory for machine learning applications is disclosed. The synapse circuit comprises a controlled variable resistance, a controlled switch connected to a contact terminal of the controlled variable resistance, and a memory cell for storing a weight variable. The memory cell is operatively connected to a control terminal of the controlled switch. A control terminal of the controlled variable resistance is configured for receiving an activation signal. The controlled variable resistance has a first resistance value and a second resistance value substantially larger than the first resistance value. A ratio of the second resistance value to the first resistance value is at least one hundred. A current, flowing through the controlled switch and the controlled variable resistance, (1) is indicative of the activation signal weighted by the stored weight variable if the controlled variable resistance is the first resistance value and (2) is smaller or equal to one picoampere at room temperature if the controlled variable resistance is adopting the second resistance value.

公开(公告)号：US20200210822A1

公开(公告)日：2020-07-02

申请号：US16723131

申请日：2019-12-20

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Mohit Gupta ,  Bharani Chakravarthy Chava ,  Wim Dehaene ,  Sushil Sakhare

IPC: G06N3/063 ,  G11C11/54 ,  G06N3/04 ,  G06F7/544

Abstract: A circuit is provided. The circuit includes a sampling circuit connectable to a multibit memory array and that samples a voltage across a sampling capacitor, a capacitance network including a plurality of capacitors and switching elements such that the capacitance network has a capacitance that depends on the configuration of the switching elements, and a buffering circuit configured to charge the capacitance of the capacitance network based on the voltage across the sampling capacitor. The circuit is configured to operate the capacitance network in a first state and a second state, wherein the capacitance in the states depends on an input value to the circuit. The circuit is also configured to charge the capacitance network in the first state and to allow the charge to redistribute within the capacitance network when it changes from the first to the second state. A system and method including such circuits are also provided.