Invention Grant
- Patent Title: Testing circuitry and methods for analog neural memory in artificial neural network
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Application No.: US16569647Application Date: 2019-09-12
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Publication No.: US11449741B2Publication Date: 2022-09-20
- Inventor: Hieu Van Tran , Thuan Vu , Stephen Trinh , Stanley Hong , Anh Ly , Steven Lemke , Nha Nguyen , Vipin Tiwari , Nhan Do
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP US
- Main IPC: G06N3/063
- IPC: G06N3/063 ; G06N3/04 ; G11C16/04 ; G11C16/10 ; G11C16/34 ; G11C16/08
Abstract:
Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.
Public/Granted literature
- US20210019608A1 Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network Public/Granted day:2021-01-21
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