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公开(公告)号：US20230244903A1
公开(公告)日：2023-08-03
申请号：US17721254
申请日：2022-04-14
发明人： Hieu Van Tran , Thuan Vu , Stanley Hong , Stephen Trinh , Anh Ly
摘要： Numerous examples are described for providing an artificial neural network system comprising an analog array and a digital array. In certain examples, an analog array and a digital array are coupled to shared bit lines. In other examples, an analog array and a digital array are coupled to separate bit lines.
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公开(公告)号：US11682459B2
公开(公告)日：2023-06-20
申请号：US17082956
申请日：2020-10-28
发明人： Hieu Van Tran , Stanley Hong , Stephen Trinh , Thuan Vu , Steven Lemke , Vipin Tiwari , Nhan Do
CPC分类号： G11C16/10 , G06N3/065 , G11C11/5628 , G11C16/0425 , G11C16/0433 , G11C16/14 , G11C16/3459
摘要： Two or more physical memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be programmed using different mechanisms. For example, one or more of the memory cells in a logical cell can be programmed using a coarse programming mechanism, one or more of the memory cells can be programmed using a fine mechanism, and one or more of the memory cells can be programmed using a tuning mechanism. This achieves extreme programming accuracy and programming speed.
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公开(公告)号：US11600321B2
公开(公告)日：2023-03-07
申请号：US16987101
申请日：2020-08-06
发明人： Hieu Van Tran , Thuan Vu , Stephen Trinh , Stanley Hong , Anh Ly , Vipin Tiwari
摘要： Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W− values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)−(W−). In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W− values.
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4.发明申请公开(公告)号：US20220374696A1
公开(公告)日：2022-11-24
申请号：US17461901
申请日：2021-08-30
发明人： Hieu Van Tran , Thuan Vu , Stanley Hong , Stephen Trinh , Anh Ly
摘要： Numerous embodiments are disclosed for splitting an array of non-volatile memory cells in an analog neural memory in a deep learning artificial neural network into multiple parts. Each part of the array interacts with certain circuitry dedicated to that part and with other circuitry that is shared with one or more other parts of the array.
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公开(公告)号：US11507642B2
公开(公告)日：2022-11-22
申请号：US16449201
申请日：2019-06-21
发明人： Hieu Van Tran , Stephen Trinh , Thuan Vu , Stanley Hong , Vipin Tiwari , Mark Reiten , Nhan Do
摘要： Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks.
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公开(公告)号：US20220172781A1
公开(公告)日：2022-06-02
申请号：US17672617
申请日：2022-02-15
发明人： Hieu Van Tran , Thuan Vu , Stanley Hong , Stephen Trinh , Anh Ly
摘要： Various embodiments of tandem row decoders are disclosed. Each embodiment of a tandem row decoder comprises a word line decoder and a control gate decoder. The tandem row decoder exhibits reduced leakage current on the word line and the control gate line when the tandem row decoder is not enabled.
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7.发明申请公开(公告)号：US20200349422A1
公开(公告)日：2020-11-05
申请号：US16449205
申请日：2019-06-21
发明人： Hieu Van Tran , Stephen Trinh , Thuan Vu , Stanley Hong , Vipin Tiwari , Mark Reiten , Nhan Do
摘要： Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks. Systems and methods are utilized for compensating for leakage and offset in the input blocks and output blocks the in analog neural memory systems.
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8.发明申请公开(公告)号：US20200242460A1
公开(公告)日：2020-07-30
申请号：US16360733
申请日：2019-03-21
发明人： Hieu Van Tran , Thuan Vu , Stephen Trinh , Stanley Hong , Anh Ly
摘要： Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed. These circuits optionally can be used for programming a non-volatile memory cell in an analog neural memory to store one of many possible values.
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9.发明公开公开(公告)号：US20240312517A1
公开(公告)日：2024-09-19
申请号：US18419079
申请日：2024-01-22
发明人： Hieu Van Tran , Thuan Vu , Stephen Trinh , Stanley Hong , Anh Ly , Steven Lemke , Vipin Tiwari , Nhan Do
CPC分类号： G11C11/54 , G06N3/065 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3418 , G11C2216/04
摘要： In one example, a method comprises erasing at the same time a word of non-volatile memory cells in an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal, by turning on an erase gate enable transistor coupled to erase gate terminals of the word of non-volatile memory cells.
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公开(公告)号：US20240079064A1
公开(公告)日：2024-03-07
申请号：US18139908
申请日：2023-04-26
发明人： Hieu Van Tran , Stanley Hong , Stephen Trinh , Thuan Vu , Steven Lemke , Vipin Tiwari , Nhan Do
CPC分类号： G11C16/10 , G06N3/065 , G11C11/5628 , G11C16/0425 , G11C16/0433 , G11C16/14 , G11C16/3459
摘要： In one example, a system comprises a neural network array of non-volatile memory cells arranged in rows and columns; and a logical cell comprising a first plurality of non-volatile memory cells in a first row of the array and a second plurality of non-volatile memory cells in a second row adjacent to the first row; wherein the first plurality of non-volatile memory cells and the second plurality of non-volatile memory cells are configured as one or more coarse cells and one or more fine cells.
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