-
公开(公告)号：US12062397B2
公开(公告)日：2024-08-13
申请号：US17585261
申请日：2022-01-26
发明人： Hieu Van Tran , Anh Ly , Kha Nguyen , Hien Pham , Duc Nguyen
CPC分类号： G11C16/16 , G11C16/102 , G11C16/26 , G11C16/30
摘要： Numerous embodiments of a transceiver for providing high voltages for use during erase or program operations in a non-volatile memory system are disclosed. In one embodiment, a transceiver comprises a PMOS transistor and a native NMOS transistor. In another embodiment, a transceiver comprises a PMOS transistor, an NMOS transistor, and a native NMOS transistor.
-
公开(公告)号：US20230244903A1
公开(公告)日：2023-08-03
申请号：US17721254
申请日：2022-04-14
发明人： Hieu Van Tran , Thuan Vu , Stanley Hong , Stephen Trinh , Anh Ly
摘要： Numerous examples are described for providing an artificial neural network system comprising an analog array and a digital array. In certain examples, an analog array and a digital array are coupled to shared bit lines. In other examples, an analog array and a digital array are coupled to separate bit lines.
-
公开(公告)号：US11600321B2
公开(公告)日：2023-03-07
申请号：US16987101
申请日：2020-08-06
发明人： Hieu Van Tran , Thuan Vu , Stephen Trinh , Stanley Hong , Anh Ly , Vipin Tiwari
摘要： Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W− values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)−(W−). In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W− values.
-
4.发明申请公开(公告)号：US20220374696A1
公开(公告)日：2022-11-24
申请号：US17461901
申请日：2021-08-30
发明人： Hieu Van Tran , Thuan Vu , Stanley Hong , Stephen Trinh , Anh Ly
摘要： Numerous embodiments are disclosed for splitting an array of non-volatile memory cells in an analog neural memory in a deep learning artificial neural network into multiple parts. Each part of the array interacts with certain circuitry dedicated to that part and with other circuitry that is shared with one or more other parts of the array.
-
公开(公告)号：US20220172781A1
公开(公告)日：2022-06-02
申请号：US17672617
申请日：2022-02-15
发明人： Hieu Van Tran , Thuan Vu , Stanley Hong , Stephen Trinh , Anh Ly
摘要： Various embodiments of tandem row decoders are disclosed. Each embodiment of a tandem row decoder comprises a word line decoder and a control gate decoder. The tandem row decoder exhibits reduced leakage current on the word line and the control gate line when the tandem row decoder is not enabled.
-
公开(公告)号：US11120881B2
公开(公告)日：2021-09-14
申请号：US17075691
申请日：2020-10-20
发明人： Hieu Van Tran , Anh Ly , Thuan Vu , Kha Nguyen , Hien Pham , Stanley Hong , Stephen T. Trinh
摘要： Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.
-
公开(公告)号：US20210082516A1
公开(公告)日：2021-03-18
申请号：US16574059
申请日：2019-09-17
发明人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
摘要： An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell.
-
公开(公告)号：US10943661B2
公开(公告)日：2021-03-09
申请号：US16550253
申请日：2019-08-25
发明人： Hieu Van Tran , Thuan Vu , Stanley Hong , Anh Ly , Vipin Tiwari , Nhan Do
IPC分类号： G11C16/04 , G06N3/08 , H01L27/11521 , H01L29/788 , G06N3/04
摘要： Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.
-
9.发明申请公开(公告)号：US20200242460A1
公开(公告)日：2020-07-30
申请号：US16360733
申请日：2019-03-21
发明人： Hieu Van Tran , Thuan Vu , Stephen Trinh , Stanley Hong , Anh Ly
摘要： Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed. These circuits optionally can be used for programming a non-volatile memory cell in an analog neural memory to store one of many possible values.
-
公开(公告)号：US20200019849A1
公开(公告)日：2020-01-16
申请号：US16151259
申请日：2018-10-03
发明人： Hieu Van Tran , Stanley Hong , Thuan Vu , Anh Ly , Hien Pham , Kha Nguyen , Han Tran
摘要： Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.
-
-
-
-
-
-
-
-
-
搜索结果
134 条记录 (耗时 0.032 秒)
