Invention Grant
- Patent Title: Method of forming interconnect structure
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Application No.: US16942789Application Date: 2020-07-30
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Publication No.: US11456211B2Publication Date: 2022-09-27
- Inventor: Bo-Jiun Lin , Tung-Ying Lee , Yu-Chao Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L21/768
- IPC: H01L21/768

Abstract:
Provided is a method of forming an interconnect structure including: forming a via; forming a first barrier layer to at least cover a top surface and a sidewall of the via; forming a first dielectric layer on the first barrier layer; performing a planarization process to remove a portion of the first dielectric layer and a portion of the first barrier layer, thereby exposing the top surface of the via; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has an opening exposing the top surface of the via; forming a blocking layer on the top surface of the via; forming a second barrier layer on the second dielectric layer; removing the blocking layer to expose the top surface of the via; and forming a conductive feature in the opening, wherein the conductive feature is in contact with the top surface of the via.
Public/Granted literature
- US20220037202A1 METHOD OF FORMING INTERCONNECT STRUCTURE Public/Granted day:2022-02-03
Information query
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