公开(公告)号：US12133476B2

公开(公告)日：2024-10-29

申请号：US18362770

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung-Ying Lee ,  Shao-Ming Yu ,  Yu-Chao Lin

IPC: H10N70/20 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10N70/011 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8828

Abstract: A device includes a bottom electrode, a first memory layer, a second memory layer, and a top electrode. The bottom electrode is over a substrate. The first memory layer is over the bottom electrode. A sidewall of the first memory layer is curved. The second memory layer is over the bottom memory layer. The top electrode is over the top memory layer.

公开(公告)号：US11818967B2

公开(公告)日：2023-11-14

申请号：US17839322

申请日：2022-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chao Lin ,  Yuan-Tien Tu ,  Shao-Ming Yu ,  Tung-Ying Lee

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/063 ,  H10N70/023 ,  H10N70/231 ,  H10N70/826

Abstract: A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer. The memory cell includes a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the phase change element. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating.

公开(公告)号：US11322619B2

公开(公告)日：2022-05-03

申请号：US16905450

申请日：2020-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chao Lin ,  Wei-Sheng Yun ,  Tung-Ying Lee

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first fin structure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure also includes a second gate structure formed over the second fin structure, and a first isolation sealing layer between the first gate structure and the second gate structure. The first isolation sealing layer is in direct contact with the first portion of the gate dielectric layer and the first portion of the filling layer.

公开(公告)号：US20210328141A1

公开(公告)日：2021-10-21

申请号：US16851111

申请日：2020-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chao Lin ,  Tung-Ying Lee

IPC: H01L45/00

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, a storage element layer, and a protective layer. The storage element layer is disposed between the bottom and top electrodes. The protective layer covers the storage element layer and the top electrode, and a material of the protective layer is derived from the storage element layer. A semiconductor device having the memory cell is also provided.

公开(公告)号：US11545490B2

公开(公告)日：2023-01-03

申请号：US16895795

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jin-Aun Ng ,  Yu-Chao Lin ,  Tung-Ying Lee

IPC: H01L29/16 ,  H01L21/324 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L21/306

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first gate-all-around FET over a substrate, and the first gate-all-around FET includes first nanostructures and a first gate stack surrounding the first nanostructures. The semiconductor structure also includes a first FinFET adjacent to the first gate-all-around FET, and the first FinFET includes a first fin structure and a second gate stack over the first fin structure. The semiconductor structure also includes a gate-cut feature interposing the first gate stack of the first gate-all-around FET and the second gate stack of the first FinFET.

公开(公告)号：US11489113B2

公开(公告)日：2022-11-01

申请号：US16851106

申请日：2020-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Ying Lee ,  Shao-Ming Yu ,  Yu-Chao Lin

IPC: H01L45/00

Abstract: A memory cell includes a storage element layer, a bottom electrode, a top electrode and a liner layer. The storage element layer has a first surface and a concaved second surface opposite to the first surface. The bottom electrode is disposed on the first surface and connected to the storage element layer. The top electrode is on the concaved second surface and connected to the storage element layer. The liner layer is surrounding the storage element layer and the top electrode.

公开(公告)号：US11456211B2

公开(公告)日：2022-09-27

申请号：US16942789

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Jiun Lin ,  Tung-Ying Lee ,  Yu-Chao Lin

IPC: H01L21/768

Abstract: Provided is a method of forming an interconnect structure including: forming a via; forming a first barrier layer to at least cover a top surface and a sidewall of the via; forming a first dielectric layer on the first barrier layer; performing a planarization process to remove a portion of the first dielectric layer and a portion of the first barrier layer, thereby exposing the top surface of the via; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has an opening exposing the top surface of the via; forming a blocking layer on the top surface of the via; forming a second barrier layer on the second dielectric layer; removing the blocking layer to expose the top surface of the via; and forming a conductive feature in the opening, wherein the conductive feature is in contact with the top surface of the via.

公开(公告)号：US11362277B2

公开(公告)日：2022-06-14

申请号：US16509105

申请日：2019-07-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chao Lin ,  Yuan-Tien Tu ,  Shao-Ming Yu ,  Tung-Ying Lee

IPC: H01L27/24 ,  H01L45/00

Abstract: A method of forming a phase change random access memory (PCRAM) device includes forming a phase change element over a bottom electrode and a top electrode over the phase change element, forming a protection layer around the phase change element, and forming a nitrogen-containing sidewall spacer layer around the protection layer after forming the protection layer.

公开(公告)号：US11342501B2

公开(公告)日：2022-05-24

申请号：US16851111

申请日：2020-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chao Lin ,  Tung-Ying Lee

IPC: H01L45/00

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, a storage element layer, and a protective layer. The storage element layer is disposed between the bottom and top electrodes. The protective layer covers the storage element layer and the top electrode, and a material of the protective layer is derived from the storage element layer. A semiconductor device having the memory cell is also provided.

公开(公告)号：US11245071B2

公开(公告)日：2022-02-08

申请号：US16737886

申请日：2020-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chao Lin ,  Carlos H. Diaz ,  Shao-Ming Yu ,  Tung-Ying Lee

IPC: H01L45/00 ,  H01L27/11519 ,  H01L27/22 ,  H01L27/24

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, an etching stop layer, a variable resistance layer, and a top electrode. The etching stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etching stop layer and in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer. A semiconductor device having the memory cell is also provided.