公开(公告)号：US20240363402A1

公开(公告)日：2024-10-31

申请号：US18769054

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Bo-Jiun Lin ,  Yu Chao Lin ,  Tung Ying Lee

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/66

CPC分类号： H01L21/76843 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76874 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L29/66795

摘要： An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

公开(公告)号：US11450563B2

公开(公告)日：2022-09-20

申请号：US17039390

申请日：2020-09-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Bo-Jiun Lin ,  Yu Chao Lin ,  Tung Ying Lee

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

摘要： An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

公开(公告)号：US20220037202A1

公开(公告)日：2022-02-03

申请号：US16942789

申请日：2020-07-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Bo-Jiun Lin ,  Tung-Ying Lee ,  Yu-Chao Lin

IPC分类号： H01L21/768

摘要： Provided is a method of forming an interconnect structure including: forming a via; forming a first barrier layer to at least cover a top surface and a sidewall of the via; forming a first dielectric layer on the first barrier layer; performing a planarization process to remove a portion of the first dielectric layer and a portion of the first barrier layer, thereby exposing the top surface of the via; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has an opening exposing the top surface of the via; forming a blocking layer on the top surface of the via; forming a second barrier layer on the second dielectric layer; removing the blocking layer to expose the top surface of the via; and forming a conductive feature in the opening, wherein the conductive feature is in contact with the top surface of the via.

公开(公告)号：US12094771B2

公开(公告)日：2024-09-17

申请号：US17883986

申请日：2022-08-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Bo-Jiun Lin ,  Yu Chao Lin ,  Tung Ying Lee

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/66

CPC分类号： H01L21/76843 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76874 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L29/66795

摘要： An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

公开(公告)号：US20220415785A1

公开(公告)日：2022-12-29

申请号：US17576137

申请日：2022-01-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tung Ying Lee ,  Bo-Jiun Lin

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532

摘要： A device includes a substrate, a dielectric layer over the substrate, and a conductive interconnect in the dielectric layer. The conductive interconnect includes a barrier/adhesion layer and a conductive layer over the barrier/adhesion layer. The barrier/adhesion layer includes a material having a chemical formula MXn, with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2.

公开(公告)号：US20220384334A1

公开(公告)日：2022-12-01

申请号：US17883986

申请日：2022-08-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Bo-Jiun Lin ,  Yu Chao Lin ,  Tung Ying Lee

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L29/66 ,  H01L23/532

摘要： An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

公开(公告)号：US11456211B2

公开(公告)日：2022-09-27

申请号：US16942789

申请日：2020-07-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Bo-Jiun Lin ,  Tung-Ying Lee ,  Yu-Chao Lin

IPC分类号： H01L21/768

摘要： Provided is a method of forming an interconnect structure including: forming a via; forming a first barrier layer to at least cover a top surface and a sidewall of the via; forming a first dielectric layer on the first barrier layer; performing a planarization process to remove a portion of the first dielectric layer and a portion of the first barrier layer, thereby exposing the top surface of the via; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has an opening exposing the top surface of the via; forming a blocking layer on the top surface of the via; forming a second barrier layer on the second dielectric layer; removing the blocking layer to expose the top surface of the via; and forming a conductive feature in the opening, wherein the conductive feature is in contact with the top surface of the via.

公开(公告)号：US20210343588A1

公开(公告)日：2021-11-04

申请号：US17039390

申请日：2020-09-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Bo-Jiun Lin ,  Yu Chao Lin ,  Tung Ying Lee

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

摘要： An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.