Invention Grant
- Patent Title: Architecture and processes to enable high capacity memory packages through memory die stacking
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Application No.: US16147742Application Date: 2018-09-29
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Publication No.: US11456281B2Publication Date: 2022-09-27
- Inventor: Yí Li , Zhiguo Qian , Prasad Ramanathan , Saikumar Jayaraman , Kemal Aygun , Hector Amador , Andrew Collins , Jianyong Xie , Shigeki Tomishima
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L25/10 ; H01L25/00

Abstract:
Embodiments include electronic packages and methods of forming such packages. An electronic package includes a memory module comprising a first memory die. The first memory die includes first interconnects with a first pad pitch and second interconnects with a second pad pitch, where the second pad pitch is less than the first pad pitch. The memory module also includes a redistribution layer below the first memory die, and a second memory die below the redistribution layer, where the second memory die has first interconnects with a first pad pitch and second interconnects with a second pad pitch. The memory module further includes a mold encapsulating the second memory die, where through mold interconnects (TMIs) provide an electrical connection from the redistribution layer to mold layer. The TMIs may be through mold vias. The TMIs may be made through a passive interposer that is encapsulated in the mold.
Information query
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