公开(公告)号：US12057413B2

公开(公告)日：2024-08-06

申请号：US16393047

申请日：2019-04-24

申请人： Intel Corporation

发明人： Lijiang Wang ,  Jianyong Xie ,  Arghya Sain ,  Xiaohong Jiang ,  Sujit Sharan ,  Kemal Aygun

IPC分类号： H01L23/66 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/66 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2924/30111

摘要： Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.

公开(公告)号：US20240222326A1

公开(公告)日：2024-07-04

申请号：US18148528

申请日：2022-12-30

申请人： Intel Corporation

发明人： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC分类号： H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H10B10/00 ,  H10B12/00 ,  H10B80/00

CPC分类号： H01L25/0655 ,  H01L23/5226 ,  H01L23/5283 ,  H10B10/12 ,  H10B12/37 ,  H10B80/00

摘要： Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit; a second IC die; a third IC die; and a package substrate. The first IC die is between the second IC die and the package substrate. The first IC die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

公开(公告)号：US11837549B2

公开(公告)日：2023-12-05

申请号：US18089542

申请日：2022-12-27

申请人： Intel Corporation

发明人： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L23/5381 ,  H01L21/486 ,  H01L21/4846 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53295 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/81 ,  H01L2924/181

摘要： Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US11817391B2

公开(公告)日：2023-11-14

申请号：US18128960

申请日：2023-03-30

申请人： Intel Corporation

发明人： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L23/532

CPC分类号： H01L23/5381 ,  H01L21/486 ,  H01L21/4846 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53295 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/81 ,  H01L2924/181

摘要： Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US11694952B2

公开(公告)日：2023-07-04

申请号：US17665315

申请日：2022-02-04

申请人： Intel Corporation

发明人： Sujit Sharan ,  Kemal Aygun ,  Zhiguo Qian ,  Yidnekachew Mekonnen ,  Zhichao Zhang ,  Jianyong Xie

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16225

摘要： Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

公开(公告)号：US11621227B2

公开(公告)日：2023-04-04

申请号：US17540141

申请日：2021-12-01

申请人： Intel Corporation

发明人： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC分类号： H01L23/52 ,  H01L21/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

摘要： Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US11545416B2

公开(公告)日：2023-01-03

申请号：US16643816

申请日：2017-09-30

申请人： Intel Corporation

发明人： Jianyong Xie ,  Yidnekachew S. Mekonnen ,  Zhiguo Qian ,  Kemal Aygun

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

摘要： An electronic device package is described. The electronic device package includes one or more dies. The electronic device package includes an interposer coupled to the one or more dies. The electronic device package also includes a package substrate coupled to the interposer. The electronic device package includes a plurality of through-silicon vias (TSVs) in at least one die of the one or more dies, or the interposer, or both. The electronic device package includes a passive equalizer structure communicatively coupled to a TSV pair in the plurality of TSVs. The passive equalizer structure is operable to minimize a level of insertion loss variation in the TSV pair.

公开(公告)号：US20220404551A1

公开(公告)日：2022-12-22

申请号：US17349305

申请日：2021-06-16

申请人： Intel Corporation

发明人： Pooya Tadayon ,  Zhichao Zhang ,  Brandon Marin ,  Tarek Ibrahim ,  Kemal Aygun ,  Stephen Smith

IPC分类号： G02B6/12 ,  G02B6/122

摘要： Integrated circuit packages may be formed having at least one optical via extending from a first surface of a package substrate to an opposing second surface of the package substrate. The at least one optical via creates an optical link between the opposing surfaces of the package substrate that enables the fabrication of a dual-sided optical multiple chip package, wherein integrated circuit devices can be attached to both surfaces of the package substrate for increased package density.

公开(公告)号：US20220270974A1

公开(公告)日：2022-08-25

申请号：US17684163

申请日：2022-03-01

申请人： INTEL CORPORATION

发明人： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC分类号： H01L23/538 ,  H01L21/762 ,  H01L21/765 ,  H01L25/065 ,  H01L29/06

摘要： An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.

公开(公告)号：US11095045B2

公开(公告)日：2021-08-17

申请号：US16493520

申请日：2017-03-30

申请人： Intel Corporation

发明人： Zhichao Zhang ,  Jiwei Sun ,  Kemal Aygun

IPC分类号： H01Q21/24 ,  H05K1/02 ,  H01P9/00

摘要： Length matching and phase matching between circuit paths of differing lengths is disclosed. Two signals are specified to arrive at respective path destinations at a predetermined time and with a predetermined phase. An IC provides a first electronic signal over a first conductive path to a first destination and a second electronic signal over a second conductive path to a second destination. A first slow wave structure comprises the first conductive path and a second slow wave structure comprises the second conductive path. The effective relative permittivity of the first slow wave structure is tuned such that the first electronic signal arrives at its destination at a first time and at a first phase, and the effective relative permittivity of the second slow wave structure is tuned such that the second electronic signal arrives at its destination at a second time and at a second phase.