Invention Grant
- Patent Title: SSD with reduced secure erase time and endurance stress
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Application No.: US16874242Application Date: 2020-05-14
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Publication No.: US11462273B2Publication Date: 2022-10-04
- Inventor: Joseph Doller , Kristopher Gaewsky , Byeongkyu Cho
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Haley Guiliano LLP
- Main IPC: G11C16/16
- IPC: G11C16/16 ; G06F3/06 ; G11C16/04

Abstract:
An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to set an erase voltage for a first block of a persistent storage media to a default erase voltage, determine if the first block of the persistent storage media is identified for a secure erase operation, and set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage. Other embodiments are disclosed and claimed.
Public/Granted literature
- US20200273525A1 SSD WITH REDUCED SECURE ERASE TIME AND ENDURANCE STRESS Public/Granted day:2020-08-27
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