公开(公告)号：US20200273525A1

公开(公告)日：2020-08-27

申请号：US16874242

申请日：2020-05-14

Applicant: Intel Corporation

Inventor： Joseph Doller ,  Kristopher Gaewsky ,  Byeongkyu Cho

IPC: G11C16/16 ,  G06F3/06

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to set an erase voltage for a first block of a persistent storage media to a default erase voltage, determine if the first block of the persistent storage media is identified for a secure erase operation, and set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage. Other embodiments are disclosed and claimed.

公开(公告)号：US11462273B2

公开(公告)日：2022-10-04

申请号：US16874242

申请日：2020-05-14

Applicant: Intel Corporation

Inventor： Joseph Doller ,  Kristopher Gaewsky ,  Byeongkyu Cho

IPC: G11C16/16 ,  G06F3/06 ,  G11C16/04

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to set an erase voltage for a first block of a persistent storage media to a default erase voltage, determine if the first block of the persistent storage media is identified for a secure erase operation, and set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage. Other embodiments are disclosed and claimed.