公开(公告)号：US20230154539A1

公开(公告)日：2023-05-18

申请号：US17528892

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Christian Mion ,  Pranav Kalavade ,  Rohit S. Shenoy ,  Xin Sun ,  Kristopher Gaewsky

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G06F3/06

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3459 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/56

Abstract: In one embodiment, an apparatus comprises a memory comprising a group of memory cells coupled to a wordline; and a controller configured to skip programming of one or more pages of the group of memory cells responsive to a sequential write operation; and program the one or more pages of the group of memory cells responsive to one or more random write commands.

公开(公告)号：US20230044991A1

公开(公告)日：2023-02-09

申请号：US17393877

申请日：2021-08-04

Applicant: Intel Corporation

Inventor： Shantanu Rajwade ,  Kartik Ganapathi ,  Rohit Shenoy ,  Kristopher Gaewsky ,  MarkAnthony Golez ,  Vivek Angoth ,  Pranav Kalavade ,  Sarvesh Gangadhar

IPC: G06F3/06

Abstract: Systems, apparatuses and methods may provide for technology that detects a request to program a NAND memory containing a plurality of dies and programs the NAND memory on a stripe-by-stripe basis, wherein each stripe spans the plurality of dies and includes multiple types of pages. The multiple types of pages may reduce program time variability across the stripes and reduce the error susceptibility of the NAND memory.

公开(公告)号：US20200273525A1

公开(公告)日：2020-08-27

申请号：US16874242

申请日：2020-05-14

Applicant: Intel Corporation

Inventor： Joseph Doller ,  Kristopher Gaewsky ,  Byeongkyu Cho

IPC: G11C16/16 ,  G06F3/06

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to set an erase voltage for a first block of a persistent storage media to a default erase voltage, determine if the first block of the persistent storage media is identified for a secure erase operation, and set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage. Other embodiments are disclosed and claimed.

公开(公告)号：US12243590B2

公开(公告)日：2025-03-04

申请号：US17528892

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Christian Mion ,  Pranav Kalavade ,  Rohit S. Shenoy ,  Xin Sun ,  Kristopher Gaewsky

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56

Abstract: In one embodiment, an apparatus comprises a memory comprising a group of memory cells coupled to a wordline; and a controller configured to skip programming of one or more pages of the group of memory cells responsive to a sequential write operation; and program the one or more pages of the group of memory cells responsive to one or more random write commands.

公开(公告)号：US11462273B2

公开(公告)日：2022-10-04

申请号：US16874242

申请日：2020-05-14

Applicant: Intel Corporation

Inventor： Joseph Doller ,  Kristopher Gaewsky ,  Byeongkyu Cho

IPC: G11C16/16 ,  G06F3/06 ,  G11C16/04

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to set an erase voltage for a first block of a persistent storage media to a default erase voltage, determine if the first block of the persistent storage media is identified for a secure erase operation, and set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage. Other embodiments are disclosed and claimed.