Invention Grant
- Patent Title: Innovative way to design silicon to overcome reticle limit
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Application No.: US16481421Application Date: 2017-04-01
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Publication No.: US11476185B2Publication Date: 2022-10-18
- Inventor: MD Altaf Hossain , Dinesh Somasekhar , Dheeraj Subbareddy
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2017/025663 WO 20170401
- International Announcement: WO2018/182755 WO 20181004
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/538 ; H01L25/065 ; H01L23/00 ; H01L25/07

Abstract:
Embodiments of the invention include a stacked die system and methods for forming such systems. In an embodiment, the stacked die system may include a first die. The first die may include a device layer and a plurality of routing layers formed over the device layer. The plurality of routing layers may be segmented into a plurality of sub regions. In an embodiment no conductive traces in the plurality of routing layers pass over a boundary between any of the plurality of sub regions. In an embodiment, the stacked die system may also include a plurality of second dies stacked over the first die. According to an embodiment, at least a two of the second dies are communicatively coupled to each other by a die to die interconnect formed entirely within a single sub region in the first die.
Public/Granted literature
- US20200176372A1 INNOVATIVE WAY TO DESIGN SILICON TO OVERCOME RETICLE LIMIT Public/Granted day:2020-06-04
Information query
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