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    Innovative Interconnect Design for Package Architecture to Improve Latency
    1.
    发明公开
    Innovative Interconnect Design for Package Architecture to Improve Latency 审中-公开

    公开(公告)号：US20240213201A1

    公开(公告)日：2024-06-27

    申请号：US18599147

    申请日：2024-03-07

    Applicant: Intel Corporation

    Inventor： MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

    IPC: H01L23/00 ,  G06F13/14 ,  G06F13/38 ,  G06F13/42 ,  H01L25/065

    CPC classification number: H01L24/18 ,  G06F13/14 ,  G06F13/385 ,  G06F13/4221 ,  G06F13/4265 ,  H01L25/0652 ,  H01L25/0655

    Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

    Techniques For Clock Signal Transmission In Integrated Circuits And Interposers
    6.
    发明申请
    Techniques For Clock Signal Transmission In Integrated Circuits And Interposers 审中-公开

    公开(公告)号：US20190227590A1

    公开(公告)日：2019-07-25

    申请号：US16367925

    申请日：2019-03-28

    Applicant: Intel Corporation

    Inventor： Jeffrey Chromczak ,  Chooi Pei Lim ,  Lai Guan Tang ,  Chee Hak Teh ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Ankireddy Nalamalpu

    IPC: G06F1/10 ,  H01L23/31

    Abstract: A circuit system includes an interposer that has a first clock network and first and second integrated circuit dies that are mounted on the interposer. The first integrated circuit die includes a phase detector circuit, an adjustable delay circuit that generates a second clock signal in response to a first clock signal received from the first clock network, and a second clock network that generates a third clock signal in response to the second clock signal. The second integrated circuit die comprises a third clock network that generates a fourth clock signal in response to the first clock signal received from the first clock network. The phase detector circuit controls a delay provided by the adjustable delay circuit to the second clock signal based on a phase comparison between phases of the third and fourth clock signals.

    Electronic chip with under-side power block
    8.
    发明授权
    Electronic chip with under-side power block 有权

    公开(公告)号：US11538753B2

    公开(公告)日：2022-12-27

    申请号：US16465255

    申请日：2016-12-30

    Applicant: Intel Corporation

    Inventor： MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Scott Gilbert ,  Jin Zhao

    IPC: H01L23/48 ,  H01L23/528 ,  H01L23/498

    Abstract: An electronic chip, system, and method includes a power block including a power source configured to provide power to components of the electronic chip and a relay circuit coupled to the power source and a ground plane. The electronic chip further includes chip package having a first major side and a second major side, the power block secured to the second major side, the chip package comprising electrical connections, disposed on the second major side, to be secured with respect to a circuit board, and interconnect circuitry, electrically coupling the power block to ground, comprising a plurality of conductive layers, a conductive through hole, electrically connecting a first pair of the plurality of conductive layers, having a first width, and a via, electrically connecting a second pair of the plurality of conductive layers, having a second width less than the first width.

    Innovative Interconnect Design for Package Architecture to Improve Latency
    10.
    发明申请
    Innovative Interconnect Design for Package Architecture to Improve Latency 有权

    公开(公告)号：US20220059491A1

    公开(公告)日：2022-02-24

    申请号：US17466396

    申请日：2021-09-03

    Applicant: Intel Corporation

    Inventor： MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

    IPC: H01L23/00 ,  G06F13/38 ,  H01L25/065 ,  G06F13/42 ,  G06F13/14

    Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

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