A storage device includes a power supply circuit that receives a power disable signal from a host device and provides a first internal voltage and a second internal voltage, a non-volatile memory including a memory device, and a storage controller that controls the non-volatile memory and includes a processor that performs a data recovery operation on data stored in the memory device and a host interface that communicates with the host device. When the power disable signal is activated at a power off time, the storage controller is powered off, the power supply circuit interrupts the first internal voltage and the second internal voltage during a reference time following the power off time, and provides the first internal voltage to the processor after the reference time has elapsed following the power off time.